Gated storage system and synchronization controller and method for multiple multi-threaded processors

Gated storage system and synchronization controller and method for multiple multi-threaded processors

A gated-storage system including multiple control interfaces, each control interface operatively competed externally to respective multithreaded processors (405A, 405B). The multithreaded processors each have a thread context running an active thread so that multiple thread contexts are running on t...

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1. Verfasser: NAVON, MOIS
Format: Patent
Sprache:eng ; fre ; ger
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CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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description A gated-storage system including multiple control interfaces, each control interface operatively competed externally to respective multithreaded processors (405A, 405B). The multithreaded processors each have a thread context running an active thread so that multiple thread contexts are running on the multithreaded processors. A memory is connected to a system-level inter-thread communications unit and shared between the multithreaded processors. The thread contexts request access to the memory by communicating multiple access requests over the control interfaces. The access requests are from any of the thread contexts within of the multithreaded processors. A single request storage is shared by the multithreaded processors. A controller stores the access requests in the single request storage within a single clock cycle.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP2187316A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP2187316A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP2187316A13</originalsourceid><addsrcrecordid>eNqNjLEKwkAQRNNYiPoP9wMpYkBtRaKWFvZhuUxM4O722F2L-PUG9QOsZnjzmGWBCxk6p8ZCDzid1BAdpRlNyQ_CaXyRjZyc52TCIUA-c4QN3LmexcVnsDEHfEtpg4C6-TQLe6iy6LpY9BQUm1-uCndu7qdricwtNJNHgrXNbVsd9nW1O1b1H8obRw5ABw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Gated storage system and synchronization controller and method for multiple multi-threaded processors</title><source>esp@cenet</source><creator>NAVON, MOIS</creator><creatorcontrib>NAVON, MOIS</creatorcontrib><description>A gated-storage system including multiple control interfaces, each control interface operatively competed externally to respective multithreaded processors (405A, 405B). The multithreaded processors each have a thread context running an active thread so that multiple thread contexts are running on the multithreaded processors. A memory is connected to a system-level inter-thread communications unit and shared between the multithreaded processors. The thread contexts request access to the memory by communicating multiple access requests over the control interfaces. The access requests are from any of the thread contexts within of the multithreaded processors. A single request storage is shared by the multithreaded processors. A controller stores the access requests in the single request storage within a single clock cycle.</description><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20100519&amp;DB=EPODOC&amp;CC=EP&amp;NR=2187316A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76292</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20100519&amp;DB=EPODOC&amp;CC=EP&amp;NR=2187316A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NAVON, MOIS</creatorcontrib><title>Gated storage system and synchronization controller and method for multiple multi-threaded processors</title><description>A gated-storage system including multiple control interfaces, each control interface operatively competed externally to respective multithreaded processors (405A, 405B). The multithreaded processors each have a thread context running an active thread so that multiple thread contexts are running on the multithreaded processors. A memory is connected to a system-level inter-thread communications unit and shared between the multithreaded processors. The thread contexts request access to the memory by communicating multiple access requests over the control interfaces. The access requests are from any of the thread contexts within of the multithreaded processors. A single request storage is shared by the multithreaded processors. A controller stores the access requests in the single request storage within a single clock cycle.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLEKwkAQRNNYiPoP9wMpYkBtRaKWFvZhuUxM4O722F2L-PUG9QOsZnjzmGWBCxk6p8ZCDzid1BAdpRlNyQ_CaXyRjZyc52TCIUA-c4QN3LmexcVnsDEHfEtpg4C6-TQLe6iy6LpY9BQUm1-uCndu7qdricwtNJNHgrXNbVsd9nW1O1b1H8obRw5ABw</recordid><startdate>20100519</startdate><enddate>20100519</enddate><creator>NAVON, MOIS</creator><scope>EVB</scope></search><sort><creationdate>20100519</creationdate><title>Gated storage system and synchronization controller and method for multiple multi-threaded processors</title><author>NAVON, MOIS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP2187316A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2010</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>NAVON, MOIS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NAVON, MOIS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Gated storage system and synchronization controller and method for multiple multi-threaded processors</title><date>2010-05-19</date><risdate>2010</risdate><abstract>A gated-storage system including multiple control interfaces, each control interface operatively competed externally to respective multithreaded processors (405A, 405B). The multithreaded processors each have a thread context running an active thread so that multiple thread contexts are running on the multithreaded processors. A memory is connected to a system-level inter-thread communications unit and shared between the multithreaded processors. The thread contexts request access to the memory by communicating multiple access requests over the control interfaces. The access requests are from any of the thread contexts within of the multithreaded processors. A single request storage is shared by the multithreaded processors. A controller stores the access requests in the single request storage within a single clock cycle.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Gated storage system and synchronization controller and method for multiple multi-threaded processors
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T10%3A13%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NAVON,%20MOIS&rft.date=2010-05-19&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP2187316A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true