MULTIPLE-CORE PROCESSOR AND SYSTEM WITH HIERARCHICAL MICROCODE STORE AND METHOD THEREFOR

A multiple-core processor having a hierarchical microcode store. A processor may include multiple processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA). Each core may include a respective local microcode un...

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Bibliographische Detailangaben

Hauptverfasser:	LIE, SEAN, SHEN, GENE, W, HOLLOWAY, BRUCE, R, BUTLER, MICHAEL, G
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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