Low voltage, high speed data latch

Low voltage, high speed data latch

Tri-stating transistors which are controlled by the latch enable lines isolate holding transistors from the latch node during setting of the latch. The tri-stating transistors are connected to the holding transistors and the latch node which allows the node to float and assume a third state during s...

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Hauptverfasser: BELZECKY, MICHAEL, LAWSON, DAVID C
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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creator BELZECKY, MICHAEL
LAWSON, DAVID C
description Tri-stating transistors which are controlled by the latch enable lines isolate holding transistors from the latch node during setting of the latch. The tri-stating transistors are connected to the holding transistors and the latch node which allows the node to float and assume a third state during setting of the latch when the latch is enabled.
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language eng ; fre ; ger
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subjects BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title Low voltage, high speed data latch
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