PROCESSOR WITH RECONFIGURABLE FLOATING POINT UNIT

A method, comprising determining, based on an indicator stored at a register or a fuse, whether a floating point unit (FPU) of a processor is to operate in full-bit mode or a reduced-bit mode, the indicator set based on power requirements of the processor; fetching a floating point instruction; and in response to determining the floating point unit is to operate in the full-bit mode, decoding the floating point instruction at a first decoder to determine a single operation; in response to determining the floating point unit is to operate in the reduced bit mode, decoding the floating point instruction at a second decoder to determine multiple operations.