IMPLEMENTING A DESIGN FLOW FOR A PROGRAMMABLE HARDWARE ELEMENT THAT INCLUDES OR IS COUPLED TO A PROCESSOR

System and method for implementing a design flow for a programmable hardware element (PHE) that includes a processor. A graphical program (GP) is received, where the GP specifies performance criteria. The GP is mapped for deployment, with a first portion targeted for execution by the processor, and...

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Hauptverfasser:	ANDRADE, Hugo A, PECK, Joseph E
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING COUNTING ELECTRIC DIGITAL DATA PROCESSING FUNCTIONAL ELEMENTS OF SUCH SYSTEMS MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS REGULATING
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creator	ANDRADE, Hugo A PECK, Joseph E
description	System and method for implementing a design flow for a programmable hardware element (PHE) that includes a processor. A graphical program (GP) is received, where the GP specifies performance criteria. The GP is mapped for deployment, with a first portion targeted for execution by the processor, and a second portion targeted for implementation in the PHE. A determination is made as to whether the graphical program meets the performance criteria. If not, the GP is remapped for deployment, including identifying and specifying the sub-portion for implementation in the PHE, thereby moving the sub-portion from the first portion to the second portion, and/or identifying and specifying the sub-portion for execution on the processor, thereby moving the sub-portion from the second portion to the first portion. The determining and remapping is repeated one or more times until the performance criteria are met. The first and second portions are deployed to the PHE.
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A graphical program (GP) is received, where the GP specifies performance criteria. The GP is mapped for deployment, with a first portion targeted for execution by the processor, and a second portion targeted for implementation in the PHE. A determination is made as to whether the graphical program meets the performance criteria. If not, the GP is remapped for deployment, including identifying and specifying the sub-portion for implementation in the PHE, thereby moving the sub-portion from the first portion to the second portion, and/or identifying and specifying the sub-portion for execution on the processor, thereby moving the sub-portion from the second portion to the first portion. The determining and remapping is repeated one or more times until the performance criteria are met. The first and second portions are deployed to the PHE.</abstract><oa>free_for_read</oa></addata></record>
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language	eng ; fre ; ger
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subjects	CALCULATING COMPUTING CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING COUNTING ELECTRIC DIGITAL DATA PROCESSING FUNCTIONAL ELEMENTS OF SUCH SYSTEMS MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS REGULATING
title	IMPLEMENTING A DESIGN FLOW FOR A PROGRAMMABLE HARDWARE ELEMENT THAT INCLUDES OR IS COUPLED TO A PROCESSOR
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