TLB LOCK INDICATOR

A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address mi...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	AUGSBURG, Victor Roberts, SARTORIUS, Thomas Andrew, BRIDGES, Jeffrey Todd, DIEFFENDERFER, James Norris
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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