HANDLING CACHE MISS IN AN INSTRUCTION CROSSING A CACHE LINE BOUNDARY

A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the secon...

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Bibliographische Detailangaben

Hauptverfasser:	SARTORIUS, Thomas, Andrew, STEMPEL, Brian, Michael, SMITH, Rodney, Wayne, BRIDGES, Jeffrey, Todd
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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