DIRECT ACCESS TO LOW-LATENCY MEMORY

DIRECT ACCESS TO LOW-LATENCY MEMORY

A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. T...

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Hauptverfasser: KESSLER, RICHARD, E, HUSSAIN, MUHAMMAD, R, BOUCHARD, GREGG, A, CARLSON, DAVID, A
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator KESSLER, RICHARD, E
HUSSAIN, MUHAMMAD, R
BOUCHARD, GREGG, A
CARLSON, DAVID, A
description A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title DIRECT ACCESS TO LOW-LATENCY MEMORY
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