Processor architecture

Processor architecture

A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimised for use in signal processing operations, in that...

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Hauptverfasser: PANESAR, GAJINDER, YOUNIS, OLFAT, KULIGOWSKI, ANDREW, DULLER, ANDREW, CLAYDON, PETER, ROBBINS, WILLIAM
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator PANESAR, GAJINDER
YOUNIS, OLFAT
KULIGOWSKI, ANDREW
DULLER, ANDREW
CLAYDON, PETER
ROBBINS, WILLIAM
description A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimised for use in signal processing operations, in that the multiple execution units of the processor are divided into groups which do not place significant restrictions on the desirable uses of the processor, because it has been determined that, in signal processing applications, it is not usually necessary for certain execution units to operate simultaneously. These execution units can therefore be grouped together, in such a way that only one of them can operate at a particular time, without significantly impacting on the operation of the device. An array is formed from multiple interconnected processors of this type.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Processor architecture
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