LATERAL BIPOLAR CMOS INTEGRATED CIRCUIT

A lateral bipolar CMOS integrated circuit having an inverter circuit including an n-channel MOS transistor and a p-channel MOS transistor, and having four terminals of: a gate input terminal Vin connected with the gates of the n-channel MOS transistor and the p-channel MOS transistor; an output terminal Vout connected with the drains of the n-channel MOS transistor and the p-channel MOS transistor; a p-type base terminal connected with a p-type substrate of the n-channel MOS transistor; and an n-type base terminal connected with an n-type substrate of the p-channel MOS transistor. The n-channel MOS transistor operates in a hybrid mode which is the hybrid of an operation mode of the MOS transistor and that of an npn lateral bipolar transistor which is inherent in the n-channel MOS transistor. The p-channel MOS transistor operates in a hybrid mode which is the hybrid of an operation mode of the MOS transistor and that of a pnp lateral bipolar transistor which is inherent in the p-channel MOS transistor.