METHOD TO IMPROVE PROFILE CONTROL AND N/P LOADING IN DUAL DOPED GATE APPLICATIONS

A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: VAHEDI, VAHID, DEL PUPPO, HELENE, MILLER, ALAN, J, KAMP, THOMAS, A, LEE, CHRIS, LIN, FRANK
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator VAHEDI, VAHID
DEL PUPPO, HELENE
MILLER, ALAN, J
KAMP, THOMAS, A
LEE, CHRIS
LIN, FRANK
description A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP1599894A2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP1599894A2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP1599894A23</originalsourceid><addsrcrecordid>eNqNyk0KwjAQhuFuXIh6h-8CIv6BWQ7JtA2kM7GNbkuRuBIt1PujCw_g5n0277w4N5xqdUgK38RWr4xvSx8YViW1GkDiIJuIoOS8VPACd6EAp5EdKkoMijF4S8mrdMtidh8eU179XBQoOdl6ncdXn6dxuOVnfvcct0djTuZAu_0fywcVzS6j</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD TO IMPROVE PROFILE CONTROL AND N/P LOADING IN DUAL DOPED GATE APPLICATIONS</title><source>esp@cenet</source><creator>VAHEDI, VAHID ; DEL PUPPO, HELENE ; MILLER, ALAN, J ; KAMP, THOMAS, A ; LEE, CHRIS ; LIN, FRANK</creator><creatorcontrib>VAHEDI, VAHID ; DEL PUPPO, HELENE ; MILLER, ALAN, J ; KAMP, THOMAS, A ; LEE, CHRIS ; LIN, FRANK</creatorcontrib><description>A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.</description><edition>7</edition><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20051130&amp;DB=EPODOC&amp;CC=EP&amp;NR=1599894A2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20051130&amp;DB=EPODOC&amp;CC=EP&amp;NR=1599894A2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>VAHEDI, VAHID</creatorcontrib><creatorcontrib>DEL PUPPO, HELENE</creatorcontrib><creatorcontrib>MILLER, ALAN, J</creatorcontrib><creatorcontrib>KAMP, THOMAS, A</creatorcontrib><creatorcontrib>LEE, CHRIS</creatorcontrib><creatorcontrib>LIN, FRANK</creatorcontrib><title>METHOD TO IMPROVE PROFILE CONTROL AND N/P LOADING IN DUAL DOPED GATE APPLICATIONS</title><description>A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyk0KwjAQhuFuXIh6h-8CIv6BWQ7JtA2kM7GNbkuRuBIt1PujCw_g5n0277w4N5xqdUgK38RWr4xvSx8YViW1GkDiIJuIoOS8VPACd6EAp5EdKkoMijF4S8mrdMtidh8eU179XBQoOdl6ncdXn6dxuOVnfvcct0djTuZAu_0fywcVzS6j</recordid><startdate>20051130</startdate><enddate>20051130</enddate><creator>VAHEDI, VAHID</creator><creator>DEL PUPPO, HELENE</creator><creator>MILLER, ALAN, J</creator><creator>KAMP, THOMAS, A</creator><creator>LEE, CHRIS</creator><creator>LIN, FRANK</creator><scope>EVB</scope></search><sort><creationdate>20051130</creationdate><title>METHOD TO IMPROVE PROFILE CONTROL AND N/P LOADING IN DUAL DOPED GATE APPLICATIONS</title><author>VAHEDI, VAHID ; DEL PUPPO, HELENE ; MILLER, ALAN, J ; KAMP, THOMAS, A ; LEE, CHRIS ; LIN, FRANK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP1599894A23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2005</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>VAHEDI, VAHID</creatorcontrib><creatorcontrib>DEL PUPPO, HELENE</creatorcontrib><creatorcontrib>MILLER, ALAN, J</creatorcontrib><creatorcontrib>KAMP, THOMAS, A</creatorcontrib><creatorcontrib>LEE, CHRIS</creatorcontrib><creatorcontrib>LIN, FRANK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>VAHEDI, VAHID</au><au>DEL PUPPO, HELENE</au><au>MILLER, ALAN, J</au><au>KAMP, THOMAS, A</au><au>LEE, CHRIS</au><au>LIN, FRANK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD TO IMPROVE PROFILE CONTROL AND N/P LOADING IN DUAL DOPED GATE APPLICATIONS</title><date>2005-11-30</date><risdate>2005</risdate><abstract>A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP1599894A2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title METHOD TO IMPROVE PROFILE CONTROL AND N/P LOADING IN DUAL DOPED GATE APPLICATIONS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T16%3A47%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=VAHEDI,%20VAHID&rft.date=2005-11-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP1599894A2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true