A METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE IN A SEMICONDUCTOR DEVICE

A method for fabricating a shallow trench isolation structure is described, in which a bottom pad oxide layer, a middle silicon nitride layer, a middle oxide layer and a top silicon nitride layer are sequentially formed on a silicon substrate. Photolithographic masking and anisotropic etching are th...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	DEGORS, NICOLAS, BARRY, TIMOTHY, M, LARSEN, BRADLEY, J, KELKAR, AMIT, S, ERICKSON, DONALD, A
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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