PSEUDO RANDOM GENERATOR
A pseudo random generator comprising a shift register comprising a first flip flop (F 0 ) and n further flip-flops (F 1 . . . Fn) each flip-flop (F 0 ) having a D input, a non-inverting output, an inverting output, and a common clock (fclk) input and the first flip-flop (F 0 ) having a set input, ea...
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creator | VAN VELDHOVEN, R HOOGZAAD, GIAN |
description | A pseudo random generator comprising a shift register comprising a first flip flop (F 0 ) and n further flip-flops (F 1 . . . Fn) each flip-flop (F 0 ) having a D input, a non-inverting output, an inverting output, and a common clock (fclk) input and the first flip-flop (F 0 ) having a set input, each of the non-inverting outputs being connected via a NOR gate ( 10 ) to the set input of the first flip-flop (F 0 ) and each of the non-inverting outputs of the flip-flops (F 0 . . . Fn) being connected to the input of the first flip-flop (F 0 ) via an XOR gate ( 11 ), characterised in that the generator comprises at least one additional logic gate ( 13, 14, 15; 17, 18, 19 ) including at least one additional flip-flop ( 14;18 ). The extra logic gates may comprise gated to toggle between the inverting end and the non-inverting outputs, or to generate an extra '0' at the output or to chop, preferably randomly, the input signal. |
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Fn) each flip-flop (F 0 ) having a D input, a non-inverting output, an inverting output, and a common clock (fclk) input and the first flip-flop (F 0 ) having a set input, each of the non-inverting outputs being connected via a NOR gate ( 10 ) to the set input of the first flip-flop (F 0 ) and each of the non-inverting outputs of the flip-flops (F 0 . . . Fn) being connected to the input of the first flip-flop (F 0 ) via an XOR gate ( 11 ), characterised in that the generator comprises at least one additional logic gate ( 13, 14, 15; 17, 18, 19 ) including at least one additional flip-flop ( 14;18 ). The extra logic gates may comprise gated to toggle between the inverting end and the non-inverting outputs, or to generate an extra '0' at the output or to chop, preferably randomly, the input signal.</description><edition>7</edition><language>eng ; fre ; ger</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20050323&DB=EPODOC&CC=EP&NR=1516430A2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20050323&DB=EPODOC&CC=EP&NR=1516430A2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>VAN VELDHOVEN, R</creatorcontrib><creatorcontrib>HOOGZAAD, GIAN</creatorcontrib><title>PSEUDO RANDOM GENERATOR</title><description>A pseudo random generator comprising a shift register comprising a first flip flop (F 0 ) and n further flip-flops (F 1 . . . Fn) each flip-flop (F 0 ) having a D input, a non-inverting output, an inverting output, and a common clock (fclk) input and the first flip-flop (F 0 ) having a set input, each of the non-inverting outputs being connected via a NOR gate ( 10 ) to the set input of the first flip-flop (F 0 ) and each of the non-inverting outputs of the flip-flops (F 0 . . . Fn) being connected to the input of the first flip-flop (F 0 ) via an XOR gate ( 11 ), characterised in that the generator comprises at least one additional logic gate ( 13, 14, 15; 17, 18, 19 ) including at least one additional flip-flop ( 14;18 ). The extra logic gates may comprise gated to toggle between the inverting end and the non-inverting outputs, or to generate an extra '0' at the output or to chop, preferably randomly, the input signal.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAPCHYNdfFXCHL0c_H3VXB39XMNcgzxD-JhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGuAYamhmYmxgaORsZEKAEAnDUfCA</recordid><startdate>20050323</startdate><enddate>20050323</enddate><creator>VAN VELDHOVEN, R</creator><creator>HOOGZAAD, GIAN</creator><scope>EVB</scope></search><sort><creationdate>20050323</creationdate><title>PSEUDO RANDOM GENERATOR</title><author>VAN VELDHOVEN, R ; HOOGZAAD, GIAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP1516430A23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2005</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>VAN VELDHOVEN, R</creatorcontrib><creatorcontrib>HOOGZAAD, GIAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>VAN VELDHOVEN, R</au><au>HOOGZAAD, GIAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PSEUDO RANDOM GENERATOR</title><date>2005-03-23</date><risdate>2005</risdate><abstract>A pseudo random generator comprising a shift register comprising a first flip flop (F 0 ) and n further flip-flops (F 1 . . . Fn) each flip-flop (F 0 ) having a D input, a non-inverting output, an inverting output, and a common clock (fclk) input and the first flip-flop (F 0 ) having a set input, each of the non-inverting outputs being connected via a NOR gate ( 10 ) to the set input of the first flip-flop (F 0 ) and each of the non-inverting outputs of the flip-flops (F 0 . . . Fn) being connected to the input of the first flip-flop (F 0 ) via an XOR gate ( 11 ), characterised in that the generator comprises at least one additional logic gate ( 13, 14, 15; 17, 18, 19 ) including at least one additional flip-flop ( 14;18 ). The extra logic gates may comprise gated to toggle between the inverting end and the non-inverting outputs, or to generate an extra '0' at the output or to chop, preferably randomly, the input signal.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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language | eng ; fre ; ger |
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subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
title | PSEUDO RANDOM GENERATOR |
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