FPGA lookup table with high speed read decoder

A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	CARBERRY, RICHARD A, BAUER, TREVOR J, YOUNG, STEVEN P
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE
Online-Zugang:	Volltext bestellen
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