Pipelining access to serialization tokens on a bus

Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a plurality of slaves. As disclosed herein, a device (e.g., a slave) may include bus logic (55) and host logic (57) coupled to the bus logic. The...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	BADI, ERIC, ZHANG, JONATHAN Y, NYCHKA, ROBERT J.P
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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