Method of forming an integrated circuit thin film resistor
A thin film resistor structure (75) is formed on a dielectric layer (60). A capping layer (90) is formed above said thin film resistor structure (75) and vias (110) are formed in the capping layer (90) using a two step etching process comprising of a dry etch process and a wet etch process. Conducti...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; fre ; ger |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | BEACH, ERIC W KWOK, SIANG PING STEINMANN, PHILIPP MAHALINGAM,MR.PUSHPA NGUYEN, ROBERT HUNG |
| description | A thin film resistor structure (75) is formed on a dielectric layer (60). A capping layer (90) is formed above said thin film resistor structure (75) and vias (110) are formed in the capping layer (90) using a two step etching process comprising of a dry etch process and a wet etch process. Conductive layers (120) are formed in the vias and form electrical contacts to the thin film resistor structure (75). |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP1463067A2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP1463067A2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP1463067A23</originalsourceid><addsrcrecordid>eNrjZLDyTS3JyE9RyE9TSMsvys3MS1dIzFPIzCtJTS9KLElNUUjOLEouzSxRKMnIzFNIy8zJVShKLc4sLskv4mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8a4BhiZmxgZm5o5GxkQoAQATFy6o</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of forming an integrated circuit thin film resistor</title><source>esp@cenet</source><creator>BEACH, ERIC W ; KWOK, SIANG PING ; STEINMANN, PHILIPP ; MAHALINGAM,MR.PUSHPA ; NGUYEN, ROBERT HUNG</creator><creatorcontrib>BEACH, ERIC W ; KWOK, SIANG PING ; STEINMANN, PHILIPP ; MAHALINGAM,MR.PUSHPA ; NGUYEN, ROBERT HUNG</creatorcontrib><description>A thin film resistor structure (75) is formed on a dielectric layer (60). A capping layer (90) is formed above said thin film resistor structure (75) and vias (110) are formed in the capping layer (90) using a two step etching process comprising of a dry etch process and a wet etch process. Conductive layers (120) are formed in the vias and form electrical contacts to the thin film resistor structure (75).</description><edition>7</edition><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; RESISTORS ; SEMICONDUCTOR DEVICES</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040929&DB=EPODOC&CC=EP&NR=1463067A2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040929&DB=EPODOC&CC=EP&NR=1463067A2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BEACH, ERIC W</creatorcontrib><creatorcontrib>KWOK, SIANG PING</creatorcontrib><creatorcontrib>STEINMANN, PHILIPP</creatorcontrib><creatorcontrib>MAHALINGAM,MR.PUSHPA</creatorcontrib><creatorcontrib>NGUYEN, ROBERT HUNG</creatorcontrib><title>Method of forming an integrated circuit thin film resistor</title><description>A thin film resistor structure (75) is formed on a dielectric layer (60). A capping layer (90) is formed above said thin film resistor structure (75) and vias (110) are formed in the capping layer (90) using a two step etching process comprising of a dry etch process and a wet etch process. Conductive layers (120) are formed in the vias and form electrical contacts to the thin film resistor structure (75).</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>RESISTORS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDyTS3JyE9RyE9TSMsvys3MS1dIzFPIzCtJTS9KLElNUUjOLEouzSxRKMnIzFNIy8zJVShKLc4sLskv4mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8a4BhiZmxgZm5o5GxkQoAQATFy6o</recordid><startdate>20040929</startdate><enddate>20040929</enddate><creator>BEACH, ERIC W</creator><creator>KWOK, SIANG PING</creator><creator>STEINMANN, PHILIPP</creator><creator>MAHALINGAM,MR.PUSHPA</creator><creator>NGUYEN, ROBERT HUNG</creator><scope>EVB</scope></search><sort><creationdate>20040929</creationdate><title>Method of forming an integrated circuit thin film resistor</title><author>BEACH, ERIC W ; KWOK, SIANG PING ; STEINMANN, PHILIPP ; MAHALINGAM,MR.PUSHPA ; NGUYEN, ROBERT HUNG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP1463067A23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2004</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>RESISTORS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BEACH, ERIC W</creatorcontrib><creatorcontrib>KWOK, SIANG PING</creatorcontrib><creatorcontrib>STEINMANN, PHILIPP</creatorcontrib><creatorcontrib>MAHALINGAM,MR.PUSHPA</creatorcontrib><creatorcontrib>NGUYEN, ROBERT HUNG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BEACH, ERIC W</au><au>KWOK, SIANG PING</au><au>STEINMANN, PHILIPP</au><au>MAHALINGAM,MR.PUSHPA</au><au>NGUYEN, ROBERT HUNG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of forming an integrated circuit thin film resistor</title><date>2004-09-29</date><risdate>2004</risdate><abstract>A thin film resistor structure (75) is formed on a dielectric layer (60). A capping layer (90) is formed above said thin film resistor structure (75) and vias (110) are formed in the capping layer (90) using a two step etching process comprising of a dry etch process and a wet etch process. Conductive layers (120) are formed in the vias and form electrical contacts to the thin film resistor structure (75).</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; fre ; ger |
| recordid | cdi_epo_espacenet_EP1463067A2 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY RESISTORS SEMICONDUCTOR DEVICES |
| title | Method of forming an integrated circuit thin film resistor |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-11T13%3A45%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BEACH,%20ERIC%20W&rft.date=2004-09-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP1463067A2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |