Interleaving method and apparatus with parallel access in linear and interleaved addressing order
The present invention relates to an interleaving method and apparatus for providing parallel access in linear and interleaved order to a predetermined number of stored data samples, especially in a turbo decoder. A memory array with a plurality of memory devices (M1 to M4) is addressed by applying a...
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Format: | Patent |
Sprache: | eng ; fre ; ger |
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