ETCH PROCESS FOR DIELECTRIC MATERIALS COMPRISING OXIDIZED ORGANO SILANE MATERIALS

The present invention provides a novel etching technique for etching a layer of C-doped silicon oxide, such as a partially oxidized organo silane material. This technique, employing CH2F2/Ar chemistry at low bias and low to intermediate pressure, provides high etch selectivity to silicon oxide and i...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: BOITEUX, YVES, PIERRE, GREGORATTO, IVANO, HSIEH, CHANG-LIN, CHEN, HUI, HUNG, HOIMAN, TANG, SUM-YEE, BETTY
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator BOITEUX, YVES, PIERRE
GREGORATTO, IVANO
HSIEH, CHANG-LIN
CHEN, HUI
HUNG, HOIMAN
TANG, SUM-YEE, BETTY
description The present invention provides a novel etching technique for etching a layer of C-doped silicon oxide, such as a partially oxidized organo silane material. This technique, employing CH2F2/Ar chemistry at low bias and low to intermediate pressure, provides high etch selectivity to silicon oxide and improved selectivity to organic photoresist. Structures including a layer of partially oxidized organo silane material (1004) deposited on a layer of silicon oxide (1002) were etched according to the novel technique, forming relatively narrow trenches (1010, 1012, 1014, 1016, 1030, 1032, 1034 and 1036) and wider trenches (1020, 1022, 1040 and 1042). The technique is also suitable for forming dual damascene structures (1152, 1154 and 1156). In additional embodiments, manufacturing systems (1410) are provided for fabricating IC structures of the present invention. These systems include a controller (1400) that is adapted for interacting with a plurality of fabricating stations (1420, 1422, 1424, 1426 and 1428).
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP1425788A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP1425788A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP1425788A13</originalsourceid><addsrcrecordid>eNrjZAh0DXH2UAgI8nd2DQ5WcPMPUnDxdPVxdQ4J8nRW8HUMcQ3ydPQJVnD29w0I8gz29HNX8I_wdPGMcnVR8A9yd_TzVwj29HH0c0Wo5WFgTUvMKU7lhdLcDApuIEt0Uwvy41OLCxKTU_NSS-JdAwxNjEzNLSwcDY2JUAIAWmAvKQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ETCH PROCESS FOR DIELECTRIC MATERIALS COMPRISING OXIDIZED ORGANO SILANE MATERIALS</title><source>esp@cenet</source><creator>BOITEUX, YVES, PIERRE ; GREGORATTO, IVANO ; HSIEH, CHANG-LIN ; CHEN, HUI ; HUNG, HOIMAN ; TANG, SUM-YEE, BETTY</creator><creatorcontrib>BOITEUX, YVES, PIERRE ; GREGORATTO, IVANO ; HSIEH, CHANG-LIN ; CHEN, HUI ; HUNG, HOIMAN ; TANG, SUM-YEE, BETTY</creatorcontrib><description>The present invention provides a novel etching technique for etching a layer of C-doped silicon oxide, such as a partially oxidized organo silane material. This technique, employing CH2F2/Ar chemistry at low bias and low to intermediate pressure, provides high etch selectivity to silicon oxide and improved selectivity to organic photoresist. Structures including a layer of partially oxidized organo silane material (1004) deposited on a layer of silicon oxide (1002) were etched according to the novel technique, forming relatively narrow trenches (1010, 1012, 1014, 1016, 1030, 1032, 1034 and 1036) and wider trenches (1020, 1022, 1040 and 1042). The technique is also suitable for forming dual damascene structures (1152, 1154 and 1156). In additional embodiments, manufacturing systems (1410) are provided for fabricating IC structures of the present invention. These systems include a controller (1400) that is adapted for interacting with a plurality of fabricating stations (1420, 1422, 1424, 1426 and 1428).</description><edition>7</edition><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040609&amp;DB=EPODOC&amp;CC=EP&amp;NR=1425788A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040609&amp;DB=EPODOC&amp;CC=EP&amp;NR=1425788A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BOITEUX, YVES, PIERRE</creatorcontrib><creatorcontrib>GREGORATTO, IVANO</creatorcontrib><creatorcontrib>HSIEH, CHANG-LIN</creatorcontrib><creatorcontrib>CHEN, HUI</creatorcontrib><creatorcontrib>HUNG, HOIMAN</creatorcontrib><creatorcontrib>TANG, SUM-YEE, BETTY</creatorcontrib><title>ETCH PROCESS FOR DIELECTRIC MATERIALS COMPRISING OXIDIZED ORGANO SILANE MATERIALS</title><description>The present invention provides a novel etching technique for etching a layer of C-doped silicon oxide, such as a partially oxidized organo silane material. This technique, employing CH2F2/Ar chemistry at low bias and low to intermediate pressure, provides high etch selectivity to silicon oxide and improved selectivity to organic photoresist. Structures including a layer of partially oxidized organo silane material (1004) deposited on a layer of silicon oxide (1002) were etched according to the novel technique, forming relatively narrow trenches (1010, 1012, 1014, 1016, 1030, 1032, 1034 and 1036) and wider trenches (1020, 1022, 1040 and 1042). The technique is also suitable for forming dual damascene structures (1152, 1154 and 1156). In additional embodiments, manufacturing systems (1410) are provided for fabricating IC structures of the present invention. These systems include a controller (1400) that is adapted for interacting with a plurality of fabricating stations (1420, 1422, 1424, 1426 and 1428).</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAh0DXH2UAgI8nd2DQ5WcPMPUnDxdPVxdQ4J8nRW8HUMcQ3ydPQJVnD29w0I8gz29HNX8I_wdPGMcnVR8A9yd_TzVwj29HH0c0Wo5WFgTUvMKU7lhdLcDApuIEt0Uwvy41OLCxKTU_NSS-JdAwxNjEzNLSwcDY2JUAIAWmAvKQ</recordid><startdate>20040609</startdate><enddate>20040609</enddate><creator>BOITEUX, YVES, PIERRE</creator><creator>GREGORATTO, IVANO</creator><creator>HSIEH, CHANG-LIN</creator><creator>CHEN, HUI</creator><creator>HUNG, HOIMAN</creator><creator>TANG, SUM-YEE, BETTY</creator><scope>EVB</scope></search><sort><creationdate>20040609</creationdate><title>ETCH PROCESS FOR DIELECTRIC MATERIALS COMPRISING OXIDIZED ORGANO SILANE MATERIALS</title><author>BOITEUX, YVES, PIERRE ; GREGORATTO, IVANO ; HSIEH, CHANG-LIN ; CHEN, HUI ; HUNG, HOIMAN ; TANG, SUM-YEE, BETTY</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP1425788A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2004</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BOITEUX, YVES, PIERRE</creatorcontrib><creatorcontrib>GREGORATTO, IVANO</creatorcontrib><creatorcontrib>HSIEH, CHANG-LIN</creatorcontrib><creatorcontrib>CHEN, HUI</creatorcontrib><creatorcontrib>HUNG, HOIMAN</creatorcontrib><creatorcontrib>TANG, SUM-YEE, BETTY</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BOITEUX, YVES, PIERRE</au><au>GREGORATTO, IVANO</au><au>HSIEH, CHANG-LIN</au><au>CHEN, HUI</au><au>HUNG, HOIMAN</au><au>TANG, SUM-YEE, BETTY</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ETCH PROCESS FOR DIELECTRIC MATERIALS COMPRISING OXIDIZED ORGANO SILANE MATERIALS</title><date>2004-06-09</date><risdate>2004</risdate><abstract>The present invention provides a novel etching technique for etching a layer of C-doped silicon oxide, such as a partially oxidized organo silane material. This technique, employing CH2F2/Ar chemistry at low bias and low to intermediate pressure, provides high etch selectivity to silicon oxide and improved selectivity to organic photoresist. Structures including a layer of partially oxidized organo silane material (1004) deposited on a layer of silicon oxide (1002) were etched according to the novel technique, forming relatively narrow trenches (1010, 1012, 1014, 1016, 1030, 1032, 1034 and 1036) and wider trenches (1020, 1022, 1040 and 1042). The technique is also suitable for forming dual damascene structures (1152, 1154 and 1156). In additional embodiments, manufacturing systems (1410) are provided for fabricating IC structures of the present invention. These systems include a controller (1400) that is adapted for interacting with a plurality of fabricating stations (1420, 1422, 1424, 1426 and 1428).</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP1425788A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title ETCH PROCESS FOR DIELECTRIC MATERIALS COMPRISING OXIDIZED ORGANO SILANE MATERIALS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-20T06%3A57%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BOITEUX,%20YVES,%20PIERRE&rft.date=2004-06-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP1425788A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true