Lateral power MOSFET

The MOS transistor of lateral structure type is formed in an n-type conductivity epitaxial layer (21) which is formed on the front face of a highly doped n-tpe conductivity substrate (22), and comprises a set of alternating drain regions (D) and source regions (S) separated by channels, a correspond...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MATTEI, SANDRA, GERMANA, ROSALIA
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator MATTEI, SANDRA
GERMANA, ROSALIA
description The MOS transistor of lateral structure type is formed in an n-type conductivity epitaxial layer (21) which is formed on the front face of a highly doped n-tpe conductivity substrate (22), and comprises a set of alternating drain regions (D) and source regions (S) separated by channels, a corresponding set of conductor regions (28,29) each covering the drain and the source regions, a metallization layer (32) connecting teh conductor regions (29) corresponding to the drain regions and covering substantially the source-drain structure. Each source region (S) comprises a highly doped n-type conductivity zone (27) in contact with the epitaxial layer (21) and with the corresponding source conductor region (28). The rear face of the substrate is covered wtih a source metallization layer (33). The zone (27) is extended substantially in the length of the source region (S), or on selected zones in the length of the source region. The MOS transistor with p-type conductivity channel also comprises the interconnected gate regions (23) formed above a thin insulator layer (24) and surrounded by an insulator layer (25), and the source regions (S) each comprising highly doped p-type conductivity zones (26). An insulator layer (30) is deposited onto the structure before the upper metallization layer (32) which is in contact with the drain metal regions (29). The types of conductivity are reversed for implementing a MOS transistor with n-type conductivity channel.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP1267413A3</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP1267413A3</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP1267413A33</originalsourceid><addsrcrecordid>eNrjZBDxSSxJLUrMUSjIL08tUvD1D3ZzDeFhYE1LzClO5YXS3AwKQFFnD93Ugvz41OKCxOTUvNSSeNcAQyMzcxNDY0djYyKUAADJQB-X</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Lateral power MOSFET</title><source>esp@cenet</source><creator>MATTEI, SANDRA ; GERMANA, ROSALIA</creator><creatorcontrib>MATTEI, SANDRA ; GERMANA, ROSALIA</creatorcontrib><description>The MOS transistor of lateral structure type is formed in an n-type conductivity epitaxial layer (21) which is formed on the front face of a highly doped n-tpe conductivity substrate (22), and comprises a set of alternating drain regions (D) and source regions (S) separated by channels, a corresponding set of conductor regions (28,29) each covering the drain and the source regions, a metallization layer (32) connecting teh conductor regions (29) corresponding to the drain regions and covering substantially the source-drain structure. Each source region (S) comprises a highly doped n-type conductivity zone (27) in contact with the epitaxial layer (21) and with the corresponding source conductor region (28). The rear face of the substrate is covered wtih a source metallization layer (33). The zone (27) is extended substantially in the length of the source region (S), or on selected zones in the length of the source region. The MOS transistor with p-type conductivity channel also comprises the interconnected gate regions (23) formed above a thin insulator layer (24) and surrounded by an insulator layer (25), and the source regions (S) each comprising highly doped p-type conductivity zones (26). An insulator layer (30) is deposited onto the structure before the upper metallization layer (32) which is in contact with the drain metal regions (29). The types of conductivity are reversed for implementing a MOS transistor with n-type conductivity channel.</description><edition>7</edition><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20030806&amp;DB=EPODOC&amp;CC=EP&amp;NR=1267413A3$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20030806&amp;DB=EPODOC&amp;CC=EP&amp;NR=1267413A3$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MATTEI, SANDRA</creatorcontrib><creatorcontrib>GERMANA, ROSALIA</creatorcontrib><title>Lateral power MOSFET</title><description>The MOS transistor of lateral structure type is formed in an n-type conductivity epitaxial layer (21) which is formed on the front face of a highly doped n-tpe conductivity substrate (22), and comprises a set of alternating drain regions (D) and source regions (S) separated by channels, a corresponding set of conductor regions (28,29) each covering the drain and the source regions, a metallization layer (32) connecting teh conductor regions (29) corresponding to the drain regions and covering substantially the source-drain structure. Each source region (S) comprises a highly doped n-type conductivity zone (27) in contact with the epitaxial layer (21) and with the corresponding source conductor region (28). The rear face of the substrate is covered wtih a source metallization layer (33). The zone (27) is extended substantially in the length of the source region (S), or on selected zones in the length of the source region. The MOS transistor with p-type conductivity channel also comprises the interconnected gate regions (23) formed above a thin insulator layer (24) and surrounded by an insulator layer (25), and the source regions (S) each comprising highly doped p-type conductivity zones (26). An insulator layer (30) is deposited onto the structure before the upper metallization layer (32) which is in contact with the drain metal regions (29). The types of conductivity are reversed for implementing a MOS transistor with n-type conductivity channel.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBDxSSxJLUrMUSjIL08tUvD1D3ZzDeFhYE1LzClO5YXS3AwKQFFnD93Ugvz41OKCxOTUvNSSeNcAQyMzcxNDY0djYyKUAADJQB-X</recordid><startdate>20030806</startdate><enddate>20030806</enddate><creator>MATTEI, SANDRA</creator><creator>GERMANA, ROSALIA</creator><scope>EVB</scope></search><sort><creationdate>20030806</creationdate><title>Lateral power MOSFET</title><author>MATTEI, SANDRA ; GERMANA, ROSALIA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP1267413A33</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2003</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MATTEI, SANDRA</creatorcontrib><creatorcontrib>GERMANA, ROSALIA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MATTEI, SANDRA</au><au>GERMANA, ROSALIA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Lateral power MOSFET</title><date>2003-08-06</date><risdate>2003</risdate><abstract>The MOS transistor of lateral structure type is formed in an n-type conductivity epitaxial layer (21) which is formed on the front face of a highly doped n-tpe conductivity substrate (22), and comprises a set of alternating drain regions (D) and source regions (S) separated by channels, a corresponding set of conductor regions (28,29) each covering the drain and the source regions, a metallization layer (32) connecting teh conductor regions (29) corresponding to the drain regions and covering substantially the source-drain structure. Each source region (S) comprises a highly doped n-type conductivity zone (27) in contact with the epitaxial layer (21) and with the corresponding source conductor region (28). The rear face of the substrate is covered wtih a source metallization layer (33). The zone (27) is extended substantially in the length of the source region (S), or on selected zones in the length of the source region. The MOS transistor with p-type conductivity channel also comprises the interconnected gate regions (23) formed above a thin insulator layer (24) and surrounded by an insulator layer (25), and the source regions (S) each comprising highly doped p-type conductivity zones (26). An insulator layer (30) is deposited onto the structure before the upper metallization layer (32) which is in contact with the drain metal regions (29). The types of conductivity are reversed for implementing a MOS transistor with n-type conductivity channel.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP1267413A3
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Lateral power MOSFET
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T23%3A30%3A03IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MATTEI,%20SANDRA&rft.date=2003-08-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP1267413A3%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true