Digital phase locked loop for embedded signal clock recovery

Digital phase locked loop for embedded signal clock recovery

A FIFO circuit assembles several digital data streams into single digital data stream. A multiplexer multiplexes the data stream with a line of video data to form an aggregate digital data stream. An independent claim is included for digital data capacity increasing method.

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1. Verfasser: BODENSCHATZ, JOHN
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
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creator BODENSCHATZ, JOHN
description A FIFO circuit assembles several digital data streams into single digital data stream. A multiplexer multiplexes the data stream with a line of video data to form an aggregate digital data stream. An independent claim is included for digital data capacity increasing method.
format Patent
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language eng ; fre ; ger
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subjects AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
title Digital phase locked loop for embedded signal clock recovery
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