Insulated gate bipolar transistor and method of making the same
A semiconductor device comprises a first base layer (1) for providing a PT-IGBT or IEGT structure, which includes a buffer layer (8) and a collector layer (9) provided in the buffer layer (8). A first activation rate, defined as the ratio of an activated first conductivity type impurity density ÄcmÜ...
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| creator | KOBAYASHI, MOTOSHIGE NOZAKI, HIDEKI |
| description | A semiconductor device comprises a first base layer (1) for providing a PT-IGBT or IEGT structure, which includes a buffer layer (8) and a collector layer (9) provided in the buffer layer (8). A first activation rate, defined as the ratio of an activated first conductivity type impurity density ÄcmÜ in the buffer layer (8) measured by means of SR analysis to a first conductivity type impurity density ÄcmÜ in the buffer layer (8) measured by means of SIMS analysis is given by 25% or more, and a second activation rate, defined as the ratio of an activated second conductivity type impurity density ÄcmÜ in the collector layer (9) measured by means of SR analysis to a second conductivity type impurity density ÄcmÜ in the collector layer (9) measured by means of SIMS analysis is given by more than 0% and 10% or less. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP1246255A3</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP1246255A3</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP1246255A33</originalsourceid><addsrcrecordid>eNrjZLD3zCsuzUksSU1RSAeSCkmZBfk5iUUKJUWJecWZxSX5RQqJeSkKuaklGfkpCvlpCrmJ2Zl56QolGakKxYm5qTwMrGmJOcWpvFCam0HBzTXE2UM3tSA_PrW4IDE5NS-1JN41wNDIxMzI1NTR2JgIJQAoQjBX</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Insulated gate bipolar transistor and method of making the same</title><source>esp@cenet</source><creator>KOBAYASHI, MOTOSHIGE ; NOZAKI, HIDEKI</creator><creatorcontrib>KOBAYASHI, MOTOSHIGE ; NOZAKI, HIDEKI</creatorcontrib><description>A semiconductor device comprises a first base layer (1) for providing a PT-IGBT or IEGT structure, which includes a buffer layer (8) and a collector layer (9) provided in the buffer layer (8). A first activation rate, defined as the ratio of an activated first conductivity type impurity density Äcm<-2>Ü in the buffer layer (8) measured by means of SR analysis to a first conductivity type impurity density Äcm<-2>Ü in the buffer layer (8) measured by means of SIMS analysis is given by 25% or more, and a second activation rate, defined as the ratio of an activated second conductivity type impurity density Äcm<-2>Ü in the collector layer (9) measured by means of SR analysis to a second conductivity type impurity density Äcm<-2>Ü in the collector layer (9) measured by means of SIMS analysis is given by more than 0% and 10% or less.</description><edition>7</edition><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040922&DB=EPODOC&CC=EP&NR=1246255A3$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040922&DB=EPODOC&CC=EP&NR=1246255A3$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KOBAYASHI, MOTOSHIGE</creatorcontrib><creatorcontrib>NOZAKI, HIDEKI</creatorcontrib><title>Insulated gate bipolar transistor and method of making the same</title><description>A semiconductor device comprises a first base layer (1) for providing a PT-IGBT or IEGT structure, which includes a buffer layer (8) and a collector layer (9) provided in the buffer layer (8). A first activation rate, defined as the ratio of an activated first conductivity type impurity density Äcm<-2>Ü in the buffer layer (8) measured by means of SR analysis to a first conductivity type impurity density Äcm<-2>Ü in the buffer layer (8) measured by means of SIMS analysis is given by 25% or more, and a second activation rate, defined as the ratio of an activated second conductivity type impurity density Äcm<-2>Ü in the collector layer (9) measured by means of SR analysis to a second conductivity type impurity density Äcm<-2>Ü in the collector layer (9) measured by means of SIMS analysis is given by more than 0% and 10% or less.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD3zCsuzUksSU1RSAeSCkmZBfk5iUUKJUWJecWZxSX5RQqJeSkKuaklGfkpCvlpCrmJ2Zl56QolGakKxYm5qTwMrGmJOcWpvFCam0HBzTXE2UM3tSA_PrW4IDE5NS-1JN41wNDIxMzI1NTR2JgIJQAoQjBX</recordid><startdate>20040922</startdate><enddate>20040922</enddate><creator>KOBAYASHI, MOTOSHIGE</creator><creator>NOZAKI, HIDEKI</creator><scope>EVB</scope></search><sort><creationdate>20040922</creationdate><title>Insulated gate bipolar transistor and method of making the same</title><author>KOBAYASHI, MOTOSHIGE ; NOZAKI, HIDEKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP1246255A33</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2004</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KOBAYASHI, MOTOSHIGE</creatorcontrib><creatorcontrib>NOZAKI, HIDEKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KOBAYASHI, MOTOSHIGE</au><au>NOZAKI, HIDEKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Insulated gate bipolar transistor and method of making the same</title><date>2004-09-22</date><risdate>2004</risdate><abstract>A semiconductor device comprises a first base layer (1) for providing a PT-IGBT or IEGT structure, which includes a buffer layer (8) and a collector layer (9) provided in the buffer layer (8). A first activation rate, defined as the ratio of an activated first conductivity type impurity density Äcm<-2>Ü in the buffer layer (8) measured by means of SR analysis to a first conductivity type impurity density Äcm<-2>Ü in the buffer layer (8) measured by means of SIMS analysis is given by 25% or more, and a second activation rate, defined as the ratio of an activated second conductivity type impurity density Äcm<-2>Ü in the collector layer (9) measured by means of SR analysis to a second conductivity type impurity density Äcm<-2>Ü in the collector layer (9) measured by means of SIMS analysis is given by more than 0% and 10% or less.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Insulated gate bipolar transistor and method of making the same |
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