SCALABLE ARCHITECTURE FOR HIGH DENSITY CPLD's HAVING TWO-LEVEL HIERARCHY OF ROUTING RESOURCES

An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segme...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: HE, XIAOJIE (WARREN), STANLEY, CLAUDIA, A, SIMON, ROBERT, A, METZGER, LARRY, R, ILGENSTEIN, KERRY, A, AGRAWAL, OM, P
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator HE, XIAOJIE (WARREN)
STANLEY, CLAUDIA, A
SIMON, ROBERT, A
METZGER, LARRY, R
ILGENSTEIN, KERRY, A
AGRAWAL, OM, P
description An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications. The large number of parallel inputs to each SLB ease implementation of 64-bit wide designs. Symmetry within the design of each segment allow for more finely-granulated implementations such as for 32 or 16-bit wide designs.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP1188241A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP1188241A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP1188241A13</originalsourceid><addsrcrecordid>eNqNi7EKwjAUALM4iPoPb3PqEHXoGtOXJhCa8vJa6SClSJxEC_H_0YIf4HTD3a3FNWrl1dkjKNLWMWruCMEEAutqCxU20fEAuvXVPoNVvWtq4EsoPPbovxHScg4QDFDoeNGEMXSkMW7F6j49ctr9uBFgkLUt0vwaU56nW3qm94itlGV5OEklj38kH4paMk8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SCALABLE ARCHITECTURE FOR HIGH DENSITY CPLD's HAVING TWO-LEVEL HIERARCHY OF ROUTING RESOURCES</title><source>esp@cenet</source><creator>HE, XIAOJIE (WARREN) ; STANLEY, CLAUDIA, A ; SIMON, ROBERT, A ; METZGER, LARRY, R ; ILGENSTEIN, KERRY, A ; AGRAWAL, OM, P</creator><creatorcontrib>HE, XIAOJIE (WARREN) ; STANLEY, CLAUDIA, A ; SIMON, ROBERT, A ; METZGER, LARRY, R ; ILGENSTEIN, KERRY, A ; AGRAWAL, OM, P</creatorcontrib><description>An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications. The large number of parallel inputs to each SLB ease implementation of 64-bit wide designs. Symmetry within the design of each segment allow for more finely-granulated implementations such as for 32 or 16-bit wide designs.</description><edition>7</edition><language>eng ; fre ; ger</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20020320&amp;DB=EPODOC&amp;CC=EP&amp;NR=1188241A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20020320&amp;DB=EPODOC&amp;CC=EP&amp;NR=1188241A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HE, XIAOJIE (WARREN)</creatorcontrib><creatorcontrib>STANLEY, CLAUDIA, A</creatorcontrib><creatorcontrib>SIMON, ROBERT, A</creatorcontrib><creatorcontrib>METZGER, LARRY, R</creatorcontrib><creatorcontrib>ILGENSTEIN, KERRY, A</creatorcontrib><creatorcontrib>AGRAWAL, OM, P</creatorcontrib><title>SCALABLE ARCHITECTURE FOR HIGH DENSITY CPLD's HAVING TWO-LEVEL HIERARCHY OF ROUTING RESOURCES</title><description>An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications. The large number of parallel inputs to each SLB ease implementation of 64-bit wide designs. Symmetry within the design of each segment allow for more finely-granulated implementations such as for 32 or 16-bit wide designs.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi7EKwjAUALM4iPoPb3PqEHXoGtOXJhCa8vJa6SClSJxEC_H_0YIf4HTD3a3FNWrl1dkjKNLWMWruCMEEAutqCxU20fEAuvXVPoNVvWtq4EsoPPbovxHScg4QDFDoeNGEMXSkMW7F6j49ctr9uBFgkLUt0vwaU56nW3qm94itlGV5OEklj38kH4paMk8</recordid><startdate>20020320</startdate><enddate>20020320</enddate><creator>HE, XIAOJIE (WARREN)</creator><creator>STANLEY, CLAUDIA, A</creator><creator>SIMON, ROBERT, A</creator><creator>METZGER, LARRY, R</creator><creator>ILGENSTEIN, KERRY, A</creator><creator>AGRAWAL, OM, P</creator><scope>EVB</scope></search><sort><creationdate>20020320</creationdate><title>SCALABLE ARCHITECTURE FOR HIGH DENSITY CPLD's HAVING TWO-LEVEL HIERARCHY OF ROUTING RESOURCES</title><author>HE, XIAOJIE (WARREN) ; STANLEY, CLAUDIA, A ; SIMON, ROBERT, A ; METZGER, LARRY, R ; ILGENSTEIN, KERRY, A ; AGRAWAL, OM, P</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP1188241A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2002</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>HE, XIAOJIE (WARREN)</creatorcontrib><creatorcontrib>STANLEY, CLAUDIA, A</creatorcontrib><creatorcontrib>SIMON, ROBERT, A</creatorcontrib><creatorcontrib>METZGER, LARRY, R</creatorcontrib><creatorcontrib>ILGENSTEIN, KERRY, A</creatorcontrib><creatorcontrib>AGRAWAL, OM, P</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HE, XIAOJIE (WARREN)</au><au>STANLEY, CLAUDIA, A</au><au>SIMON, ROBERT, A</au><au>METZGER, LARRY, R</au><au>ILGENSTEIN, KERRY, A</au><au>AGRAWAL, OM, P</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SCALABLE ARCHITECTURE FOR HIGH DENSITY CPLD's HAVING TWO-LEVEL HIERARCHY OF ROUTING RESOURCES</title><date>2002-03-20</date><risdate>2002</risdate><abstract>An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications. The large number of parallel inputs to each SLB ease implementation of 64-bit wide designs. Symmetry within the design of each segment allow for more finely-granulated implementations such as for 32 or 16-bit wide designs.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP1188241A1
source esp@cenet
subjects BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title SCALABLE ARCHITECTURE FOR HIGH DENSITY CPLD's HAVING TWO-LEVEL HIERARCHY OF ROUTING RESOURCES
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T10%3A06%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HE,%20XIAOJIE%20(WARREN)&rft.date=2002-03-20&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP1188241A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true