A flash memory array

A layout and method for FLASH memory with no SAS process. The layout involves a source contact (91) that connects the source regions of a series of memory cells (11) and forms the source line (24). The source contact is formed using a hard mask insulator layer (100) as a part of the memory cell gate...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	XIA, JIE, MEHRAD, FREIDOON, AMBROSE, THOMAS M
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES
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