A flash memory array

A flash memory array

A layout and method for FLASH memory with no SAS process. The layout involves a source contact (91) that connects the source regions of a series of memory cells (11) and forms the source line (24). The source contact is formed using a hard mask insulator layer (100) as a part of the memory cell gate...

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Hauptverfasser: XIA, JIE, MEHRAD, FREIDOON, AMBROSE, THOMAS M
Format: Patent
Sprache:eng ; fre ; ger
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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creator XIA, JIE
MEHRAD, FREIDOON
AMBROSE, THOMAS M
description A layout and method for FLASH memory with no SAS process. The layout involves a source contact (91) that connects the source regions of a series of memory cells (11) and forms the source line (24). The source contact is formed using a hard mask insulator layer (100) as a part of the memory cell gate stack (110), (115) which insulates the control gate (18) during source contact (91) formation.
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
title A flash memory array
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