MATRIX SWITCH
A matrix switch comprises a matrix switch main body (2), a preprocessing block (1) provided on an input side of the matrix switch main body (2), and a postprocessing block (3) provided on an output side of the matrix switch main body (2), wherein each of the preprocessing block (1), the matrix switc...
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| creator | DOBASHI, KYOSUKE IDE, KAZUHIKO |
| description | A matrix switch comprises a matrix switch main body (2), a preprocessing block (1) provided on an input side of the matrix switch main body (2), and a postprocessing block (3) provided on an output side of the matrix switch main body (2), wherein each of the preprocessing block (1), the matrix switch main body (2) and the postprocessing block (3) comprises a circuit, which parallel-converts a line input with each setting bit width, performs a bit stream operation in the setting bit width, serially converts it, and performs line output, respectively, and the matrix switch main body (2) is divided into the setting bit width parallel-converted with the preprocessing block (1) and switching-control is performed. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP1061700A4</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP1061700A4</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP1061700A43</originalsourceid><addsrcrecordid>eNrjZOD1dQwJ8oxQCA73DHH24GFgTUvMKU7lhdLcDApurkBx3dSC_PjU4oLE5NS81JJ41wBDAzNDcwMDRxNjIpQAAHwoHEc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MATRIX SWITCH</title><source>esp@cenet</source><creator>DOBASHI, KYOSUKE ; IDE, KAZUHIKO</creator><creatorcontrib>DOBASHI, KYOSUKE ; IDE, KAZUHIKO</creatorcontrib><description>A matrix switch comprises a matrix switch main body (2), a preprocessing block (1) provided on an input side of the matrix switch main body (2), and a postprocessing block (3) provided on an output side of the matrix switch main body (2), wherein each of the preprocessing block (1), the matrix switch main body (2) and the postprocessing block (3) comprises a circuit, which parallel-converts a line input with each setting bit width, performs a bit stream operation in the setting bit width, serially converts it, and performs line output, respectively, and the matrix switch main body (2) is divided into the setting bit width parallel-converted with the preprocessing block (1) and switching-control is performed.</description><edition>7</edition><language>eng ; fre ; ger</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2009</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090729&DB=EPODOC&CC=EP&NR=1061700A4$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090729&DB=EPODOC&CC=EP&NR=1061700A4$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DOBASHI, KYOSUKE</creatorcontrib><creatorcontrib>IDE, KAZUHIKO</creatorcontrib><title>MATRIX SWITCH</title><description>A matrix switch comprises a matrix switch main body (2), a preprocessing block (1) provided on an input side of the matrix switch main body (2), and a postprocessing block (3) provided on an output side of the matrix switch main body (2), wherein each of the preprocessing block (1), the matrix switch main body (2) and the postprocessing block (3) comprises a circuit, which parallel-converts a line input with each setting bit width, performs a bit stream operation in the setting bit width, serially converts it, and performs line output, respectively, and the matrix switch main body (2) is divided into the setting bit width parallel-converted with the preprocessing block (1) and switching-control is performed.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOD1dQwJ8oxQCA73DHH24GFgTUvMKU7lhdLcDApurkBx3dSC_PjU4oLE5NS81JJ41wBDAzNDcwMDRxNjIpQAAHwoHEc</recordid><startdate>20090729</startdate><enddate>20090729</enddate><creator>DOBASHI, KYOSUKE</creator><creator>IDE, KAZUHIKO</creator><scope>EVB</scope></search><sort><creationdate>20090729</creationdate><title>MATRIX SWITCH</title><author>DOBASHI, KYOSUKE ; IDE, KAZUHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP1061700A43</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2009</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>DOBASHI, KYOSUKE</creatorcontrib><creatorcontrib>IDE, KAZUHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DOBASHI, KYOSUKE</au><au>IDE, KAZUHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MATRIX SWITCH</title><date>2009-07-29</date><risdate>2009</risdate><abstract>A matrix switch comprises a matrix switch main body (2), a preprocessing block (1) provided on an input side of the matrix switch main body (2), and a postprocessing block (3) provided on an output side of the matrix switch main body (2), wherein each of the preprocessing block (1), the matrix switch main body (2) and the postprocessing block (3) comprises a circuit, which parallel-converts a line input with each setting bit width, performs a bit stream operation in the setting bit width, serially converts it, and performs line output, respectively, and the matrix switch main body (2) is divided into the setting bit width parallel-converted with the preprocessing block (1) and switching-control is performed.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| language | eng ; fre ; ger |
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| subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | MATRIX SWITCH |
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