Interruptable multiple execution unit processing during operations utilizing multiple assignment of registers

A method of operating a multiple execution unit microprocessor in a software pipelined loop (Figure 2c) is disclosed. This method allows the microprocessor to respond to interrupt requests and other runtime conditions during execution of a software pipelined loop utilizing multiple assignment of registers. In one embodiment, the method comprises branching out of the software pipelined loop (Kernel), upon occurrence of an interrupt request, to an interrupt epilog (Epilog) that consumes in-flight register values and sets the interrupt return pointer to the address of an interrupt prolog. The interrupt is then taken. The interrupt prolog is a subset of the loop prolog (Prolog), and restores the processor to an operational state equivalent to one that would have existed had the interrupt not been taken. Loop execution is then resumed without data loss or corruption.