COORDINATING THE ISSUE OF INSTRUCTIONS IN A PARALLEL INSTRUCTION PROCESSING SYSTEM

In a microprocessor, apparatus and method coordinate the fetch and issue of instructions by rotating multiple, fetched instructions into an issue order prior to issuance and dispatching selected of the issue ordered instructions. The rotate and dispatch block including a mixer for mixing newly fetch...

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Bibliographische Detailangaben

Hauptverfasser:	SAVKAR, SUNIL, SAJJADIAN, FARNAD, SHEN, GENE, W, SHEBANOW, MICHAEL, C
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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