Method for increasing the data storage rate of a computer system
A method for controlling the flow of data from a longword size bus to a cache (28) of a computer system during a two clock cycle period of time, the cache (28) having a quadword size data access path over which a quadword of data is written in a single clock cycle. During a first cycle of the two cl...
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| creator | FOSSUM TRYGGVE SALETT RONALD M MANLEY DWIGHT P HETHERINGTON RICKY C WEBB JR DAVID A |
| description | A method for controlling the flow of data from a longword size bus to a cache (28) of a computer system during a two clock cycle period of time, the cache (28) having a quadword size data access path over which a quadword of data is written in a single clock cycle. During a first cycle of the two clock cycle period of time, a first longword of data is delivered over the bus to the cache (28) and is stored in a buffer. The cache (28) has a cache block address to which the data is to be written to obtain a hit signal when the addressed cache block is free to receive data. In response to the hit signal, a quadword context signal is generated indicating that the first longword of data is to be paired with a second longword of data to form a quadword of data and a quadword aligned address signal is generated indicating that the quadword of data is to be stored at an address aligned with the cache block address. The second longword together with the first longword are stored in the addressed cache block by passing them over different portions of the quadword data access path. |
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During a first cycle of the two clock cycle period of time, a first longword of data is delivered over the bus to the cache (28) and is stored in a buffer. The cache (28) has a cache block address to which the data is to be written to obtain a hit signal when the addressed cache block is free to receive data. In response to the hit signal, a quadword context signal is generated indicating that the first longword of data is to be paired with a second longword of data to form a quadword of data and a quadword aligned address signal is generated indicating that the quadword of data is to be stored at an address aligned with the cache block address. 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During a first cycle of the two clock cycle period of time, a first longword of data is delivered over the bus to the cache (28) and is stored in a buffer. The cache (28) has a cache block address to which the data is to be written to obtain a hit signal when the addressed cache block is free to receive data. In response to the hit signal, a quadword context signal is generated indicating that the first longword of data is to be paired with a second longword of data to form a quadword of data and a quadword aligned address signal is generated indicating that the quadword of data is to be stored at an address aligned with the cache block address. The second longword together with the first longword are stored in the addressed cache block by passing them over different portions of the quadword data access path.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Method for increasing the data storage rate of a computer system |
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