Memory multiplexing system for a high definition video decoder

A memory system which uses a main memory that stores and fetches data as 192-bit data values includes a data formatter. The formatter combines successive received 8-bit values into a 192-bit value and combines successive received 32-bit values into a distinct 192-bit value in an output buffer memory. In addition, the memory system includes a first latch-multiplexer which provides selected 192-bit words fetched from an input buffer memory as a sequence of 8-bit values and a second data multiplexer which provides other 192-bit words from the input buffer memory as a sequence of 32-bit values. A memory controller sequences the operation of the input buffers and the first and second multiplexers to send data to and receive data from the respective 8-bit and 32-bit data channels at rates which do not exceed a predetermined worst-case set of rates.