Method for high-speed testing a semiconductor device

A method for high speed testing a semiconductor device, such as a processor (102), involves providing an array probe assembly (160) which includes a test substrate (164) having integrated circuits (104, 106) mounted thereon. A first subset of interconnects (112) of the test substrate electrically connect the integrated circuits to the device under test. A second subset of interconnects (116) electrically connect the device under test to an external tester (120). A third subset of interconnects (110) are used to electrically connect the integrated circuits to the external tester. Interconnects (110) are used to selectively communicate information in a high speed manner, while interconnects (112) are used to selectively communicate information in a low speed manner. Thus, the integrated circuits on the test substrate enable testing of a device at frequencies higher than the tester frequency, and further eliminate the need for pin-for-pin compatibility between the tester and the device under test.