Antenna array with processing delay as a multiple of the time slot duration
An apparatus for performance improvement of a burst mode digital wireless receiver comprises a processing circuit for processing a plurality of received signals and providing a processed signal and a delay circuit for introducing a predetermined delay to the processed signal. The delay circuit is co...
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| creator | MARTIN, CAROL CATALANO WINTERS, JACK HARRIMAN GOLDEN, GLENN DAVID |
| description | An apparatus for performance improvement of a burst mode digital wireless receiver comprises a processing circuit for processing a plurality of received signals and providing a processed signal and a delay circuit for introducing a predetermined delay to the processed signal. The delay circuit is coupled to the processing circuit. The predetermined delay is such that the processed signal is delayed to correspond with a later data burst. The processing circuit weights and combines the received signals, where the processing circuit reduces a mean squared error of an output signal. The processing circuit weights and combines the received signals using a predetermined symbol pattern within a sync sequence within a time slot. |
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| language | eng ; fre ; ger |
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| subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY MULTIPLEX COMMUNICATION TRANSMISSION TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | Antenna array with processing delay as a multiple of the time slot duration |
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