Integrated circuit chip having gate array book personalisation using local interconnect

A gate array book layout for an integrated circuit chip is disclosed in which a local interconnect layer provides N-well and P-well contact straps extending substantially along the entire width of said gate array book across the top and bottom edges thereof. This enables efficient electrical connections between the various connection points located within the book. In particular, primarily vertical strips of local interconnect are used to connect contact points which exist at or near the same layer as the local interconnect layer. By using local interconnect in this manner, metal-1 layer usage is significantly reduced thereby allowing for a more efficient integrated circuit chip design.