A method of fabricating a DRAM with increased capacitance

A method for forming a dynamic random access memory with increased capacitance includes preparing (36) ultra-fine particles in a microemulsion. The particles are deposited (38) on the lower electrode layer of the memory cell. A micro-villus pattern is then formed (40) on the lower electrode layer, u...

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Hauptverfasser: CRENSHAW, DARIUS L, KUMAR, PROMOD
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creator CRENSHAW, DARIUS L
KUMAR, PROMOD
description A method for forming a dynamic random access memory with increased capacitance includes preparing (36) ultra-fine particles in a microemulsion. The particles are deposited (38) on the lower electrode layer of the memory cell. A micro-villus pattern is then formed (40) on the lower electrode layer, using the particles as a mask. A layer of HSG polysilicon may then be deposited (42) on the micro-villus pattern. A dielectric and upper electrode are then formed (44) overlying the lower electrode to form a storage capacitor for the dynamic random access memory.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP0767488A3</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP0767488A3</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP0767488A33</originalsourceid><addsrcrecordid>eNrjZLB0VMhNLcnIT1HIT1NIS0wqykxOLMnMS1dIVHAJcvRVKM8syVDIzEsuSk0sTk1RSE4sSEzOLEnMS07lYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxUB1qXmpJfGuAQbmZuYmFhaOxsZEKAEAW3wtSA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>A method of fabricating a DRAM with increased capacitance</title><source>esp@cenet</source><creator>CRENSHAW, DARIUS L ; KUMAR, PROMOD</creator><creatorcontrib>CRENSHAW, DARIUS L ; KUMAR, PROMOD</creatorcontrib><description>A method for forming a dynamic random access memory with increased capacitance includes preparing (36) ultra-fine particles in a microemulsion. The particles are deposited (38) on the lower electrode layer of the memory cell. A micro-villus pattern is then formed (40) on the lower electrode layer, using the particles as a mask. A layer of HSG polysilicon may then be deposited (42) on the micro-villus pattern. A dielectric and upper electrode are then formed (44) overlying the lower electrode to form a storage capacitor for the dynamic random access memory.</description><edition>6</edition><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1998</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19980909&amp;DB=EPODOC&amp;CC=EP&amp;NR=0767488A3$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19980909&amp;DB=EPODOC&amp;CC=EP&amp;NR=0767488A3$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CRENSHAW, DARIUS L</creatorcontrib><creatorcontrib>KUMAR, PROMOD</creatorcontrib><title>A method of fabricating a DRAM with increased capacitance</title><description>A method for forming a dynamic random access memory with increased capacitance includes preparing (36) ultra-fine particles in a microemulsion. The particles are deposited (38) on the lower electrode layer of the memory cell. A micro-villus pattern is then formed (40) on the lower electrode layer, using the particles as a mask. A layer of HSG polysilicon may then be deposited (42) on the micro-villus pattern. A dielectric and upper electrode are then formed (44) overlying the lower electrode to form a storage capacitor for the dynamic random access memory.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1998</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB0VMhNLcnIT1HIT1NIS0wqykxOLMnMS1dIVHAJcvRVKM8syVDIzEsuSk0sTk1RSE4sSEzOLEnMS07lYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxUB1qXmpJfGuAQbmZuYmFhaOxsZEKAEAW3wtSA</recordid><startdate>19980909</startdate><enddate>19980909</enddate><creator>CRENSHAW, DARIUS L</creator><creator>KUMAR, PROMOD</creator><scope>EVB</scope></search><sort><creationdate>19980909</creationdate><title>A method of fabricating a DRAM with increased capacitance</title><author>CRENSHAW, DARIUS L ; KUMAR, PROMOD</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0767488A33</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>1998</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CRENSHAW, DARIUS L</creatorcontrib><creatorcontrib>KUMAR, PROMOD</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CRENSHAW, DARIUS L</au><au>KUMAR, PROMOD</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>A method of fabricating a DRAM with increased capacitance</title><date>1998-09-09</date><risdate>1998</risdate><abstract>A method for forming a dynamic random access memory with increased capacitance includes preparing (36) ultra-fine particles in a microemulsion. The particles are deposited (38) on the lower electrode layer of the memory cell. A micro-villus pattern is then formed (40) on the lower electrode layer, using the particles as a mask. A layer of HSG polysilicon may then be deposited (42) on the micro-villus pattern. A dielectric and upper electrode are then formed (44) overlying the lower electrode to form a storage capacitor for the dynamic random access memory.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title A method of fabricating a DRAM with increased capacitance
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T03%3A11%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CRENSHAW,%20DARIUS%20L&rft.date=1998-09-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP0767488A3%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true