Early completion of floating-point operations during load/store multiple operations

A method and apparatus in a superscalar microprocessor (10) for early completion of floating-point instructions prior to a previous load/store multiple instruction is provided. The microprocessor's load/store execution unit (28) loads or stores data to or from the general purpose registers (32), and the microprocessor's dispatch unit (20) dispatches instructions to a plurality of execution units, including the load/store execution unit (28) and the floating point execution unit (30). The method comprises the dispatch unit (20) dispatching a multi-register instruction to the load/store unit (28) to begin execution of the multi-register instruction, wherein the multi-register instruction, such as a store multiple or a load multiple, stores or loads data from more than one of the plurality of general purpose registers (32) to memory, and further, prior to the multi-register instruction finishing execution in the load/store unit (28), the dispatch unit (20) dispatches a floating-point instruction, which is dependent upon source operand data stored in one or more floating-point registers (36) of the plurality of floating point registers, to the floating-point execution unit (30), wherein the dispatched floating-point instruction completes execution prior to the multi-register instruction finishing execution.