High efficiency quasi-vertical DMOS in MOS or BICMOS process
A QVDMOS array 10 has QVDMOS devices with a silicide contact 42 to source 35 and body tie 36. The body tie 36 is enclosed by the source at the surface and extends beneath but not beyond the annular source 35. The QVDMOS is formed during a number of process steps that simultaneously form regions in N...
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| creator | PEARCE, LAWRENCE G |
| description | A QVDMOS array 10 has QVDMOS devices with a silicide contact 42 to source 35 and body tie 36. The body tie 36 is enclosed by the source at the surface and extends beneath but not beyond the annular source 35. The QVDMOS is formed during a number of process steps that simultaneously form regions in NMOS, PMOS and bipolar devices. |
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| language | eng ; fre ; ger |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | High efficiency quasi-vertical DMOS in MOS or BICMOS process |
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