Memory device with programmable self-refreshing and testing methods therefore

The programmable refresh circuit includes a self-timed oscillator that outputs a clocking signal, and a programmable pattern generator that outputs a first signal pattern and a second signal pattern. The first signal pattern is fed to a counter circuit which also receives the clocking signal and outputs a signal pulse whenever the count driven by the clocking signal reaches a digital pattern representation corresp. to the first signal pattern generated by the programmable pattern generator. Refresh control logic is connected to receive the pulse signal and respond to it by refreshing a portion of the memory array of the semiconductor memory device. The second signal pattern is employed by the refresh control logic to set the wait state interval for the self-refresh operation. The semiconductor device receives row address strobe (RAS) signal and column address strobe (CAS) signal from the control system connected to it, and signal initiating self-refresh comprises CAS before RAS transition of signals received from control systems.