PACKET PROCESSING METHOD AND APPARATUS

A method and apparatus for processing a data packet, for delivery to a designated location, store selective portions of the packet header in a high speed cache memory to increase processing speed and hence throughput for a packet delivery system. The apparatus and method receive the packets from a d...

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1. Verfasser:	HARRIMAN, EDWARD, S., JR
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator	HARRIMAN, EDWARD, S., JR
description	A method and apparatus for processing a data packet, for delivery to a designated location, store selective portions of the packet header in a high speed cache memory to increase processing speed and hence throughput for a packet delivery system. The apparatus and method receive the packets from a data channel source and store portions of the header in cache, and at least the remainder of each data packet is stored in a slower speed memory. A CPU accesses the stored header portion of each packet in cache for necessary protocol and destination information processing of the data packet. The header portions are then overwritten with new data and combined with the remainder of the data packet stored in slower speed memory for transmission to the next packet destination. Preferably, the address at which the remainder portions are stored in slower speed memory determine the cache addresses at which the header portion is stored in high speed cache memory.
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The apparatus and method receive the packets from a data channel source and store portions of the header in cache, and at least the remainder of each data packet is stored in a slower speed memory. A CPU accesses the stored header portion of each packet in cache for necessary protocol and destination information processing of the data packet. The header portions are then overwritten with new data and combined with the remainder of the data packet stored in slower speed memory for transmission to the next packet destination. Preferably, the address at which the remainder portions are stored in slower speed memory determine the cache addresses at which the header portion is stored in high speed cache memory.</description><edition>5</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1995</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19951011&DB=EPODOC&CC=EP&NR=0606368A4$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25555,76308</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19951011&DB=EPODOC&CC=EP&NR=0606368A4$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HARRIMAN, EDWARD, S., JR</creatorcontrib><title>PACKET PROCESSING METHOD AND APPARATUS</title><description>A method and apparatus for processing a data packet, for delivery to a designated location, store selective portions of the packet header in a high speed cache memory to increase processing speed and hence throughput for a packet delivery system. The apparatus and method receive the packets from a data channel source and store portions of the header in cache, and at least the remainder of each data packet is stored in a slower speed memory. A CPU accesses the stored header portion of each packet in cache for necessary protocol and destination information processing of the data packet. The header portions are then overwritten with new data and combined with the remainder of the data packet stored in slower speed memory for transmission to the next packet destination. Preferably, the address at which the remainder portions are stored in slower speed memory determine the cache addresses at which the header portion is stored in high speed cache memory.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1995</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFALcHT2dg1RCAjyd3YNDvb0c1fwdQ3x8HdRcPQD4oAAxyDHkNBgHgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oS7xpgYGZgZmxm4WhiTIQSAH5zIy8</recordid><startdate>19951011</startdate><enddate>19951011</enddate><creator>HARRIMAN, EDWARD, S., JR</creator><scope>EVB</scope></search><sort><creationdate>19951011</creationdate><title>PACKET PROCESSING METHOD AND APPARATUS</title><author>HARRIMAN, EDWARD, S., JR</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0606368A43</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1995</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>HARRIMAN, EDWARD, S., JR</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HARRIMAN, EDWARD, S., JR</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PACKET PROCESSING METHOD AND APPARATUS</title><date>1995-10-11</date><risdate>1995</risdate><abstract>A method and apparatus for processing a data packet, for delivery to a designated location, store selective portions of the packet header in a high speed cache memory to increase processing speed and hence throughput for a packet delivery system. The apparatus and method receive the packets from a data channel source and store portions of the header in cache, and at least the remainder of each data packet is stored in a slower speed memory. A CPU accesses the stored header portion of each packet in cache for necessary protocol and destination information processing of the data packet. The header portions are then overwritten with new data and combined with the remainder of the data packet stored in slower speed memory for transmission to the next packet destination. Preferably, the address at which the remainder portions are stored in slower speed memory determine the cache addresses at which the header portion is stored in high speed cache memory.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record>
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language	eng
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title	PACKET PROCESSING METHOD AND APPARATUS
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