Integrated data processing system including CPU core and parallel, independently operating DSP module
The present invention is directed to various features of an integrated data processing system that includes a general purpose (GP) CPU core for processing data in accordance with a GP instruction set and a digital signal processor (DSP) module for processing data in accordance with command-list code...
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creator | COHEN, RONNY SHIMONY, ILAN SANDBANK, ALBERTO EPSTEIN, LEV INTRATER, GIDEON KATZRI, LIOR DORON, MOSHE GREENFELD, ZVI AFEK, YACHIN CARMON, IDDO VINER, OMRI LEVITAN, RAYA YOMTOV, SIDI FRAENKEL, ITAEL TZADIK, YEHEZKEL GREISS, ISRAEL BIRENBAUM, ANDY TSADIK, MEIR INTRATER, AMOS OZ, OVED |
description | The present invention is directed to various features of an integrated data processing system that includes a general purpose (GP) CPU core for processing data in accordance with a GP instruction set and a digital signal processor (DSP) module for processing data in accordance with command-list code. The DSP module is operable to execute the command-list code independent of and in parallel with execution of the GP instruction set by the CPU core. |
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The DSP module is operable to execute the command-list code independent of and in parallel with execution of the GP instruction set by the CPU core.</description><edition>6</edition><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1999</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990421&DB=EPODOC&CC=EP&NR=0545581B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990421&DB=EPODOC&CC=EP&NR=0545581B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>COHEN, RONNY</creatorcontrib><creatorcontrib>SHIMONY, ILAN</creatorcontrib><creatorcontrib>SANDBANK, ALBERTO</creatorcontrib><creatorcontrib>EPSTEIN, LEV</creatorcontrib><creatorcontrib>INTRATER, GIDEON</creatorcontrib><creatorcontrib>KATZRI, LIOR</creatorcontrib><creatorcontrib>DORON, MOSHE</creatorcontrib><creatorcontrib>GREENFELD, ZVI</creatorcontrib><creatorcontrib>AFEK, YACHIN</creatorcontrib><creatorcontrib>CARMON, IDDO</creatorcontrib><creatorcontrib>VINER, OMRI</creatorcontrib><creatorcontrib>LEVITAN, RAYA</creatorcontrib><creatorcontrib>YOMTOV, SIDI</creatorcontrib><creatorcontrib>FRAENKEL, ITAEL</creatorcontrib><creatorcontrib>TZADIK, YEHEZKEL</creatorcontrib><creatorcontrib>GREISS, ISRAEL</creatorcontrib><creatorcontrib>BIRENBAUM, ANDY</creatorcontrib><creatorcontrib>TSADIK, MEIR</creatorcontrib><creatorcontrib>INTRATER, AMOS</creatorcontrib><creatorcontrib>OZ, OVED</creatorcontrib><title>Integrated data processing system including CPU core and parallel, independently operating DSP module</title><description>The present invention is directed to various features of an integrated data processing system that includes a general purpose (GP) CPU core for processing data in accordance with a GP instruction set and a digital signal processor (DSP) module for processing data in accordance with command-list code. The DSP module is operable to execute the command-list code independent of and in parallel with execution of the GP instruction set by the CPU core.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1999</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzEEKwjAUBNBsXIh6h38ABYsGXFsruiuo6_JJpqXwm4QkXfT2tuAB3MzA8Ji1wtNldJEzLFnOTCF6g5R611GaUsZAvTMy2mUo6w8ZH0HsLAWOLALZz8AiYA6XZSIfMN8t_PaqafB2FGzVqmVJ2P16o-hevcvHAcE3SIENHHJT1Ud91vpSXIvTH-QLm24-lA</recordid><startdate>19990421</startdate><enddate>19990421</enddate><creator>COHEN, RONNY</creator><creator>SHIMONY, ILAN</creator><creator>SANDBANK, ALBERTO</creator><creator>EPSTEIN, LEV</creator><creator>INTRATER, GIDEON</creator><creator>KATZRI, LIOR</creator><creator>DORON, MOSHE</creator><creator>GREENFELD, ZVI</creator><creator>AFEK, YACHIN</creator><creator>CARMON, IDDO</creator><creator>VINER, OMRI</creator><creator>LEVITAN, RAYA</creator><creator>YOMTOV, SIDI</creator><creator>FRAENKEL, ITAEL</creator><creator>TZADIK, YEHEZKEL</creator><creator>GREISS, ISRAEL</creator><creator>BIRENBAUM, ANDY</creator><creator>TSADIK, MEIR</creator><creator>INTRATER, AMOS</creator><creator>OZ, OVED</creator><scope>EVB</scope></search><sort><creationdate>19990421</creationdate><title>Integrated data processing system including CPU core and parallel, independently operating DSP module</title><author>COHEN, RONNY ; SHIMONY, ILAN ; SANDBANK, ALBERTO ; EPSTEIN, LEV ; INTRATER, GIDEON ; KATZRI, LIOR ; DORON, MOSHE ; GREENFELD, ZVI ; AFEK, YACHIN ; CARMON, IDDO ; VINER, OMRI ; LEVITAN, RAYA ; YOMTOV, SIDI ; FRAENKEL, ITAEL ; TZADIK, YEHEZKEL ; GREISS, ISRAEL ; BIRENBAUM, ANDY ; TSADIK, MEIR ; INTRATER, AMOS ; OZ, OVED</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0545581B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>1999</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>COHEN, RONNY</creatorcontrib><creatorcontrib>SHIMONY, ILAN</creatorcontrib><creatorcontrib>SANDBANK, ALBERTO</creatorcontrib><creatorcontrib>EPSTEIN, LEV</creatorcontrib><creatorcontrib>INTRATER, GIDEON</creatorcontrib><creatorcontrib>KATZRI, LIOR</creatorcontrib><creatorcontrib>DORON, MOSHE</creatorcontrib><creatorcontrib>GREENFELD, ZVI</creatorcontrib><creatorcontrib>AFEK, YACHIN</creatorcontrib><creatorcontrib>CARMON, IDDO</creatorcontrib><creatorcontrib>VINER, OMRI</creatorcontrib><creatorcontrib>LEVITAN, RAYA</creatorcontrib><creatorcontrib>YOMTOV, SIDI</creatorcontrib><creatorcontrib>FRAENKEL, ITAEL</creatorcontrib><creatorcontrib>TZADIK, YEHEZKEL</creatorcontrib><creatorcontrib>GREISS, ISRAEL</creatorcontrib><creatorcontrib>BIRENBAUM, ANDY</creatorcontrib><creatorcontrib>TSADIK, MEIR</creatorcontrib><creatorcontrib>INTRATER, AMOS</creatorcontrib><creatorcontrib>OZ, OVED</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>COHEN, RONNY</au><au>SHIMONY, ILAN</au><au>SANDBANK, ALBERTO</au><au>EPSTEIN, LEV</au><au>INTRATER, GIDEON</au><au>KATZRI, LIOR</au><au>DORON, MOSHE</au><au>GREENFELD, ZVI</au><au>AFEK, YACHIN</au><au>CARMON, IDDO</au><au>VINER, OMRI</au><au>LEVITAN, RAYA</au><au>YOMTOV, SIDI</au><au>FRAENKEL, ITAEL</au><au>TZADIK, YEHEZKEL</au><au>GREISS, ISRAEL</au><au>BIRENBAUM, ANDY</au><au>TSADIK, MEIR</au><au>INTRATER, AMOS</au><au>OZ, OVED</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated data processing system including CPU core and parallel, independently operating DSP module</title><date>1999-04-21</date><risdate>1999</risdate><abstract>The present invention is directed to various features of an integrated data processing system that includes a general purpose (GP) CPU core for processing data in accordance with a GP instruction set and a digital signal processor (DSP) module for processing data in accordance with command-list code. The DSP module is operable to execute the command-list code independent of and in parallel with execution of the GP instruction set by the CPU core.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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language | eng ; fre ; ger |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
title | Integrated data processing system including CPU core and parallel, independently operating DSP module |
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