Planar FET-SEED integrated circuits

Structure and method for fabricating FETs and quantum well diodes on the same semi-insulating substrate where the FET is provided with enhanced protection from spurious voltages. The structure uses a deeply buried p-layer (17) in a semi-insulating substrate (14) partitioned to isolate the FET portio...

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Bibliographische Detailangaben
Hauptverfasser: CHIROVSKY, LEO MARIA FREISHYN, D'ASARO, LUCIAN ARTHUR, PEI, SHIN-SHEM, WOODWARD, TED KIRK
Format: Patent
Sprache:eng ; fre ; ger
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Zusammenfassung:Structure and method for fabricating FETs and quantum well diodes on the same semi-insulating substrate where the FET is provided with enhanced protection from spurious voltages. The structure uses a deeply buried p-layer (17) in a semi-insulating substrate (14) partitioned to isolate the FET portion (40) of the substrate. The same buried p-layer can be partitioned to provide the p-regions of quantum well diodes (30).