ARBITRATION CIRCUIT FOR A MULTIMEDIA SYSTEM
The invention is an N-bit arbitration circuit which includes N bit subcircuits, each of which provides a single bit output signal of an N-bit arbitration signal. The bit subcircuits include a more significant bit subcircuit and a least significant bit subcircuit. The more significant bit subcircuit...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | The invention is an N-bit arbitration circuit which includes N bit subcircuits, each of which provides a single bit output signal of an N-bit arbitration signal. The bit subcircuits include a more significant bit subcircuit and a least significant bit subcircuit. The more significant bit subcircuit includes a gate, which receives a more significant bit priority signal and an arbitration enable signal and provides a more significant bit of the N-bit arbitration signal, and a pipeline circuit, which receives the more significant bit priority signal, the arbitration enable signal and the more significant bit and provides a pipelined arbitration enable signal based upon the more significant bit priority signal, the arbitration enable signal and the more significant bit. The least significant bit subcircuit includes a gate, which receives a least significant bit priority signal and the pipelined arbitration enable signal and provides a least significant bit output signal of the N-bit arbitration circuit output signal, and a source enable circuit, which receives the least significant bit arbitration indication signal and the pipelined arbitration enable signal and provides a source enable signal based upon the least significant bit arbitration indication signal and the pipelined arbitration signal. |
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