High-speed multi-port FIFO buffer circuit

A buffer memory for use in the output queue of a packet switching network is described. The buffer consists of two separate memories (160, 170, 260, 270) connected through a multiplexer (310) to the output of the switch. A memory access control (120, 220) processes the incoming data which arrives on...

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Bibliographische Detailangaben

Hauptverfasser:	DENZEL, WOLFGANG EMIL, ENGBERSEN, ANTONIUS J.P
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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