DRAM HAVING EXTENDED REFRESH TIME

A DRAM is described including a plurality of operable storage cells (50), each cell (50) including a capacitance for storing a charge indicative of data. The charge tends to dissipate below an acceptable level after a predetermined time interval T1 for a majority of the operable cells and for a minority of the operable cells, it dissipates below the acceptable level after a shorter time interval T2. The time between DRAM refresh cycles is adjusted so as to be greater than time interval T2. In addition to the plurality of redundant storage cells (50) the DRAM comprises: a decoder (64) for receiving the address of an operable memory cell and providing a first output if the address indicates one of the operable cells of the minority of cells and a second output if the address indicates one of the operable cells of the majority. A switching circuit (56, 58, 72) is responsive to the first output to enable access of a redundant storage cell and to prevent access of the minority storage cell. In a preferred embodiment, the redundant storage cells (50) are configured as static storage circuits.