Sampling clock generating circuit

Sampling clock generating circuit

A circuit generates a sampling clock which is used for the A-D conversion of a video signal. A master clock produced by a frequency synthesizer (1) is demultiplied in frequency at dividing ratio NS by a programmable frequency demultiplier (2) which is reset by the horizontal sync signal. The resulti...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: MAESHIMA, KAZUYA
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator MAESHIMA, KAZUYA
description A circuit generates a sampling clock which is used for the A-D conversion of a video signal. A master clock produced by a frequency synthesizer (1) is demultiplied in frequency at dividing ratio NS by a programmable frequency demultiplier (2) which is reset by the horizontal sync signal. The resulting sampling clock can have one of various frequencies depending on the combination of the frequency dividing ratio NM of the frequency synthesizer (1) and the frequency dividing ratio NS of the programmable frequency demultiplier (2) so that it is fit for various video signals.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP0454955A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP0454955A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP0454955A13</originalsourceid><addsrcrecordid>eNrjZFAMTswtyMnMS1dIzslPzlZIT81LLUosAQtkFiWXZpbwMLCmJeYUp_JCaW4GBTfXEGcP3dSC_PjU4oLEZKCWknjXAAMTUxNLU1NHQ2MilAAASGklbg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Sampling clock generating circuit</title><source>esp@cenet</source><creator>MAESHIMA, KAZUYA</creator><creatorcontrib>MAESHIMA, KAZUYA</creatorcontrib><description>A circuit generates a sampling clock which is used for the A-D conversion of a video signal. A master clock produced by a frequency synthesizer (1) is demultiplied in frequency at dividing ratio NS by a programmable frequency demultiplier (2) which is reset by the horizontal sync signal. The resulting sampling clock can have one of various frequencies depending on the combination of the frequency dividing ratio NM of the frequency synthesizer (1) and the frequency dividing ratio NS of the programmable frequency demultiplier (2) so that it is fit for various video signals.</description><language>eng ; fre ; ger</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><creationdate>1991</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19911106&amp;DB=EPODOC&amp;CC=EP&amp;NR=0454955A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19911106&amp;DB=EPODOC&amp;CC=EP&amp;NR=0454955A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MAESHIMA, KAZUYA</creatorcontrib><title>Sampling clock generating circuit</title><description>A circuit generates a sampling clock which is used for the A-D conversion of a video signal. A master clock produced by a frequency synthesizer (1) is demultiplied in frequency at dividing ratio NS by a programmable frequency demultiplier (2) which is reset by the horizontal sync signal. The resulting sampling clock can have one of various frequencies depending on the combination of the frequency dividing ratio NM of the frequency synthesizer (1) and the frequency dividing ratio NS of the programmable frequency demultiplier (2) so that it is fit for various video signals.</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1991</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAMTswtyMnMS1dIzslPzlZIT81LLUosAQtkFiWXZpbwMLCmJeYUp_JCaW4GBTfXEGcP3dSC_PjU4oLEZKCWknjXAAMTUxNLU1NHQ2MilAAASGklbg</recordid><startdate>19911106</startdate><enddate>19911106</enddate><creator>MAESHIMA, KAZUYA</creator><scope>EVB</scope></search><sort><creationdate>19911106</creationdate><title>Sampling clock generating circuit</title><author>MAESHIMA, KAZUYA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0454955A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>1991</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>PICTORIAL COMMUNICATION, e.g. TELEVISION</topic><toplevel>online_resources</toplevel><creatorcontrib>MAESHIMA, KAZUYA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MAESHIMA, KAZUYA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Sampling clock generating circuit</title><date>1991-11-06</date><risdate>1991</risdate><abstract>A circuit generates a sampling clock which is used for the A-D conversion of a video signal. A master clock produced by a frequency synthesizer (1) is demultiplied in frequency at dividing ratio NS by a programmable frequency demultiplier (2) which is reset by the horizontal sync signal. The resulting sampling clock can have one of various frequencies depending on the combination of the frequency dividing ratio NM of the frequency synthesizer (1) and the frequency dividing ratio NS of the programmable frequency demultiplier (2) so that it is fit for various video signals.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP0454955A1
source esp@cenet
subjects AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
title Sampling clock generating circuit
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T22%3A55%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MAESHIMA,%20KAZUYA&rft.date=1991-11-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP0454955A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true