Semiconductor memory device including nonvolatile memory cells, enhancement type load transistors, and peripheral circuits having enhancement type transistors
A semiconductor memory device comprises a non-volatile memory cell array (70) having a plurality of memory cells (71), enhancement type load transistors (73, 73') having a threshold voltage, and at least one peripheral circuit, such as level shifters (74), column decoders (76), etc., including...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; fre ; ger |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | UEMURA, TERUO KAWASE, YUKIO |
| description | A semiconductor memory device comprises a non-volatile memory cell array (70) having a plurality of memory cells (71), enhancement type load transistors (73, 73') having a threshold voltage, and at least one peripheral circuit, such as level shifters (74), column decoders (76), etc., including enhancement type transistors having a threshold voltage. For increasing the writing speed of the memory cells (71), the threshold voltage of the enhancement type load transistors (73, 73') is set so that it is different from that of the enhancement type transistors of the peripheral circuit. For example, the threshold voltage of the enhancement type load transistors (73, 73') is lower than that of the enhancement type transistors of the peripheral circuit. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP0442335B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP0442335B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP0442335B13</originalsourceid><addsrcrecordid>eNqNzEGKwkAQheFsZiGOd6gDjKBGL6BkmOXAuJei-mkKOtVNdyeQy3jWiaAguHH1Nt_7Z9X1D51KMNdLCYk6dCGN5DCogNTE907tQhZsCJ6LejyMwPv8RbCWTdDBCpUxgnxgRyWxZc1TciJsjiKSxhaJPYkm6bVkanm4tV8KT-fP6uPMPmNx33lF383x8LNEDCfkyAJDOTW_q-12U9e7_bp-g_wDGEtWFw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor memory device including nonvolatile memory cells, enhancement type load transistors, and peripheral circuits having enhancement type transistors</title><source>esp@cenet</source><creator>UEMURA, TERUO ; KAWASE, YUKIO</creator><creatorcontrib>UEMURA, TERUO ; KAWASE, YUKIO</creatorcontrib><description>A semiconductor memory device comprises a non-volatile memory cell array (70) having a plurality of memory cells (71), enhancement type load transistors (73, 73') having a threshold voltage, and at least one peripheral circuit, such as level shifters (74), column decoders (76), etc., including enhancement type transistors having a threshold voltage. For increasing the writing speed of the memory cells (71), the threshold voltage of the enhancement type load transistors (73, 73') is set so that it is different from that of the enhancement type transistors of the peripheral circuit. For example, the threshold voltage of the enhancement type load transistors (73, 73') is lower than that of the enhancement type transistors of the peripheral circuit.</description><edition>6</edition><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>1996</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19961127&DB=EPODOC&CC=EP&NR=0442335B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19961127&DB=EPODOC&CC=EP&NR=0442335B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>UEMURA, TERUO</creatorcontrib><creatorcontrib>KAWASE, YUKIO</creatorcontrib><title>Semiconductor memory device including nonvolatile memory cells, enhancement type load transistors, and peripheral circuits having enhancement type transistors</title><description>A semiconductor memory device comprises a non-volatile memory cell array (70) having a plurality of memory cells (71), enhancement type load transistors (73, 73') having a threshold voltage, and at least one peripheral circuit, such as level shifters (74), column decoders (76), etc., including enhancement type transistors having a threshold voltage. For increasing the writing speed of the memory cells (71), the threshold voltage of the enhancement type load transistors (73, 73') is set so that it is different from that of the enhancement type transistors of the peripheral circuit. For example, the threshold voltage of the enhancement type load transistors (73, 73') is lower than that of the enhancement type transistors of the peripheral circuit.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1996</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzEGKwkAQheFsZiGOd6gDjKBGL6BkmOXAuJei-mkKOtVNdyeQy3jWiaAguHH1Nt_7Z9X1D51KMNdLCYk6dCGN5DCogNTE907tQhZsCJ6LejyMwPv8RbCWTdDBCpUxgnxgRyWxZc1TciJsjiKSxhaJPYkm6bVkanm4tV8KT-fP6uPMPmNx33lF383x8LNEDCfkyAJDOTW_q-12U9e7_bp-g_wDGEtWFw</recordid><startdate>19961127</startdate><enddate>19961127</enddate><creator>UEMURA, TERUO</creator><creator>KAWASE, YUKIO</creator><scope>EVB</scope></search><sort><creationdate>19961127</creationdate><title>Semiconductor memory device including nonvolatile memory cells, enhancement type load transistors, and peripheral circuits having enhancement type transistors</title><author>UEMURA, TERUO ; KAWASE, YUKIO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0442335B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>1996</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>UEMURA, TERUO</creatorcontrib><creatorcontrib>KAWASE, YUKIO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>UEMURA, TERUO</au><au>KAWASE, YUKIO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor memory device including nonvolatile memory cells, enhancement type load transistors, and peripheral circuits having enhancement type transistors</title><date>1996-11-27</date><risdate>1996</risdate><abstract>A semiconductor memory device comprises a non-volatile memory cell array (70) having a plurality of memory cells (71), enhancement type load transistors (73, 73') having a threshold voltage, and at least one peripheral circuit, such as level shifters (74), column decoders (76), etc., including enhancement type transistors having a threshold voltage. For increasing the writing speed of the memory cells (71), the threshold voltage of the enhancement type load transistors (73, 73') is set so that it is different from that of the enhancement type transistors of the peripheral circuit. For example, the threshold voltage of the enhancement type load transistors (73, 73') is lower than that of the enhancement type transistors of the peripheral circuit.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; fre ; ger |
| recordid | cdi_epo_espacenet_EP0442335B1 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
| title | Semiconductor memory device including nonvolatile memory cells, enhancement type load transistors, and peripheral circuits having enhancement type transistors |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T00%3A23%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=UEMURA,%20TERUO&rft.date=1996-11-27&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP0442335B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |