A LOGIC SIMULATION USING A HARDWARE ACCELERATOR TOGETHER WITH AN AUTOMATED ERROR EVENT ISOLATION AND TRACE FACILITY

Software simulators of logic design circuits run slowly but are capable of providing very finely detailed error trace analyses. On the other hand, hardware accelerators (70, 200) operating to perform similar functions are very fast in their execution but are not capable of practically isolating erro...

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Bibliographische Detailangaben

Hauptverfasser:	CHU, SALINA SAU-YUE, SHELDON, ROBERT GEORGE, LACKEY, DAVID ERNEST, DEIBERT, GEORGE ROBERT, ACKERMAN, DENNIS FRANK, BENDER, DAVID RANDA, STRANKO, THOMAS ANDREW, HALLOCK, GARY GRIFFEN
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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