Burst mode read implementation

Burst mode read implementation

A microcomputer system memory controller architecture and method permits high speed access to data in the system memory (102), allowing the system memory (102) to operate in a burst mode. The architecture and method utilizes a system memory controller (108, 208) capable of performing the addressing...

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Hauptverfasser: LANG, MARILYN J, BASSETT, CAROL E, CAMPBELL, ROBERT G, BEGUR, SRIDHAR
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator LANG, MARILYN J
BASSETT, CAROL E
CAMPBELL, ROBERT G
BEGUR, SRIDHAR
description A microcomputer system memory controller architecture and method permits high speed access to data in the system memory (102), allowing the system memory (102) to operate in a burst mode. The architecture and method utilizes a system memory controller (108, 208) capable of performing the addressing of the system memory (102) without constant supervision by the microprocessor (106, 206). The microprocessor (106, 206) and the system memory (102) electrically communicate by way of a host bus (204). The memory controller (108, 208) generates second addresses corresponding to data locations in system memory (102) upon receipt of the initial address of a set of first addresses from the microprocessor (106, 206). Accordingly, the microprocessor (106, 206) can access data in the system memory (102) at an extremely fast rate when attempting to read in a burst mode. High speed access is accomplished without the need for an external cache.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Burst mode read implementation
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