Data processing system with instruction tag apparatus
A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included...
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| creator | HICKS, TROY NEAL NGUYENPHU, MYHONG |
| description | A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit. |
| format | Patent |
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Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.</description><edition>5</edition><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1995</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950222&DB=EPODOC&CC=EP&NR=0437044B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25551,76302</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950222&DB=EPODOC&CC=EP&NR=0437044B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HICKS, TROY NEAL</creatorcontrib><creatorcontrib>NGUYENPHU, MYHONG</creatorcontrib><title>Data processing system with instruction tag apparatus</title><description>A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1995</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDB1SSxJVCgoyk9OLS7OzEtXKK4sLknNVSjPLMlQyMwrLikqTS7JzM9TKElMV0gsKEgsSiwpLeZhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGuAQYmxuYGJiZOhsZEKAEATtEtWQ</recordid><startdate>19950222</startdate><enddate>19950222</enddate><creator>HICKS, TROY NEAL</creator><creator>NGUYENPHU, MYHONG</creator><scope>EVB</scope></search><sort><creationdate>19950222</creationdate><title>Data processing system with instruction tag apparatus</title><author>HICKS, TROY NEAL ; NGUYENPHU, MYHONG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0437044B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>1995</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>HICKS, TROY NEAL</creatorcontrib><creatorcontrib>NGUYENPHU, MYHONG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HICKS, TROY NEAL</au><au>NGUYENPHU, MYHONG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Data processing system with instruction tag apparatus</title><date>1995-02-22</date><risdate>1995</risdate><abstract>A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record> |
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| language | eng ; fre ; ger |
| recordid | cdi_epo_espacenet_EP0437044B1 |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Data processing system with instruction tag apparatus |
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