Contact structure for semiconductor integrated circuits
A method for forming a via contact for devices having multilayer metallization is provided wherein a sacrificial layer (14) is formed over a bottom interconnect layer (12,13), and an interlayer dielectric (16) is formed on the sacrificial layer (14). A via is etched in the interlayer dielectric (16)...
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creator | SELLERS, JAMES A MATTOX, ROBERT J WILSON, SYD ROBERT |
description | A method for forming a via contact for devices having multilayer metallization is provided wherein a sacrificial layer (14) is formed over a bottom interconnect layer (12,13), and an interlayer dielectric (16) is formed on the sacrificial layer (14). A via is etched in the interlayer dielectric (16), exposing the sacrificial layer (14). The sacrificial layer (14) is isotropically etched to expose an area (23) of the interconnect metal (12,13) that is larger than the area of the via and a via metallization (21) is selectively formed on the interconnect metal (13) by chemical vapor deposition so that the via, including a void created by the isotropic etch of the sacrificial layer (14), is filled with the via metallization (21), thereby providing a contact area to the bottom interconnect metal (12,13) which is larger than the via metallization itself. |
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A via is etched in the interlayer dielectric (16), exposing the sacrificial layer (14). The sacrificial layer (14) is isotropically etched to expose an area (23) of the interconnect metal (12,13) that is larger than the area of the via and a via metallization (21) is selectively formed on the interconnect metal (13) by chemical vapor deposition so that the via, including a void created by the isotropic etch of the sacrificial layer (14), is filled with the via metallization (21), thereby providing a contact area to the bottom interconnect metal (12,13) which is larger than the via metallization itself.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1990</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19901114&DB=EPODOC&CC=EP&NR=0397462A2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19901114&DB=EPODOC&CC=EP&NR=0397462A2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SELLERS, JAMES A</creatorcontrib><creatorcontrib>MATTOX, ROBERT J</creatorcontrib><creatorcontrib>WILSON, SYD ROBERT</creatorcontrib><title>Contact structure for semiconductor integrated circuits</title><description>A method for forming a via contact for devices having multilayer metallization is provided wherein a sacrificial layer (14) is formed over a bottom interconnect layer (12,13), and an interlayer dielectric (16) is formed on the sacrificial layer (14). A via is etched in the interlayer dielectric (16), exposing the sacrificial layer (14). The sacrificial layer (14) is isotropically etched to expose an area (23) of the interconnect metal (12,13) that is larger than the area of the via and a via metallization (21) is selectively formed on the interconnect metal (13) by chemical vapor deposition so that the via, including a void created by the isotropic etch of the sacrificial layer (14), is filled with the via metallization (21), thereby providing a contact area to the bottom interconnect metal (12,13) which is larger than the via metallization itself.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1990</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDB3zs8rSUwuUSguKSpNLiktSlVIyy9SKE7NzUzOz0sBCgF5mXklqelFiSWpKQrJmUXJpZklxTwMrGmJOcWpvFCam0HBzTXE2UM3tSA_PrW4IDE5NS-1JN41wMDY0tzEzMjRyJgIJQDe4y52</recordid><startdate>19901114</startdate><enddate>19901114</enddate><creator>SELLERS, JAMES A</creator><creator>MATTOX, ROBERT J</creator><creator>WILSON, SYD ROBERT</creator><scope>EVB</scope></search><sort><creationdate>19901114</creationdate><title>Contact structure for semiconductor integrated circuits</title><author>SELLERS, JAMES A ; MATTOX, ROBERT J ; WILSON, SYD ROBERT</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0397462A23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>1990</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SELLERS, JAMES A</creatorcontrib><creatorcontrib>MATTOX, ROBERT J</creatorcontrib><creatorcontrib>WILSON, SYD ROBERT</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SELLERS, JAMES A</au><au>MATTOX, ROBERT J</au><au>WILSON, SYD ROBERT</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Contact structure for semiconductor integrated circuits</title><date>1990-11-14</date><risdate>1990</risdate><abstract>A method for forming a via contact for devices having multilayer metallization is provided wherein a sacrificial layer (14) is formed over a bottom interconnect layer (12,13), and an interlayer dielectric (16) is formed on the sacrificial layer (14). A via is etched in the interlayer dielectric (16), exposing the sacrificial layer (14). The sacrificial layer (14) is isotropically etched to expose an area (23) of the interconnect metal (12,13) that is larger than the area of the via and a via metallization (21) is selectively formed on the interconnect metal (13) by chemical vapor deposition so that the via, including a void created by the isotropic etch of the sacrificial layer (14), is filled with the via metallization (21), thereby providing a contact area to the bottom interconnect metal (12,13) which is larger than the via metallization itself.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Contact structure for semiconductor integrated circuits |
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