PROCESS FOR FORMING HIGH-VOLTAGE AND LOW-VOLTAGE CMOS TRANSISTORS ON A SINGLE INTEGRATED CIRCUIT CHIP

A process for forming both low-voltage CMOS transistors and high-voltage CMOS transistors on a common integrated circuit chip uses a common implantation and drive-in step to form both the n-type well (174,374) of each PMOS transistor and the n-type drain extension well (274) of each lightly-doped dr...

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Hauptverfasser:	PARRISH, JACK DUANA, SCHNABEL, DOUGLAS ROBERT, MANN, JONATHAN DOUGLAS, KOSIAK, WALTER KIRK, ROWLANDS, PAUL RUSSELL, III
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	PARRISH, JACK DUANA SCHNABEL, DOUGLAS ROBERT MANN, JONATHAN DOUGLAS KOSIAK, WALTER KIRK ROWLANDS, PAUL RUSSELL, III
description	A process for forming both low-voltage CMOS transistors and high-voltage CMOS transistors on a common integrated circuit chip uses a common implantation and drive-in step to form both the n-type well (174,374) of each PMOS transistor and the n-type drain extension well (274) of each lightly-doped drain (LDD) NMOS transistor and a separate implant and drive-in to form the p-type drain extension well (182) of each LDD PMOS transistor.
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subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	PROCESS FOR FORMING HIGH-VOLTAGE AND LOW-VOLTAGE CMOS TRANSISTORS ON A SINGLE INTEGRATED CIRCUIT CHIP
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