Data communication arrangement with embedded matrix switch
Modems, data service units (109-111), application modules (108, 112, 114, 115) and other data communication devices (102-106), installed in a common equipment cabinet, are interconnected by way of a time division multiplexed bus (RB, WB, TSA, TYPE). Time slots assigned to the various devices recur a...
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creator | DOUSKALIS, WILLIAM |
description | Modems, data service units (109-111), application modules (108, 112, 114, 115) and other data communication devices (102-106), installed in a common equipment cabinet, are interconnected by way of a time division multiplexed bus (RB, WB, TSA, TYPE). Time slots assigned to the various devices recur at a number of regularly-spaced access periods across each time division multiplex frame. The rate at which the access periods occur and the total number of access periods that make up each frame are chosen in such a way as to accomodate a mix of devices having respective bus access rates wherein there is at least one pair of rates for which neither rate of the pair is a multiple of the other. The process of allocating access periods to the time slots is carried out using a known lemma to identify linear Diophantine equation solutions. |
format | Patent |
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Time slots assigned to the various devices recur at a number of regularly-spaced access periods across each time division multiplex frame. The rate at which the access periods occur and the total number of access periods that make up each frame are chosen in such a way as to accomodate a mix of devices having respective bus access rates wherein there is at least one pair of rates for which neither rate of the pair is a multiple of the other. The process of allocating access periods to the time slots is carried out using a known lemma to identify linear Diophantine equation solutions.</description><edition>5</edition><language>eng ; fre ; ger</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; MULTIPLEX COMMUNICATION ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1995</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950104&DB=EPODOC&CC=EP&NR=0353946B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950104&DB=EPODOC&CC=EP&NR=0353946B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DOUSKALIS, WILLIAM</creatorcontrib><title>Data communication arrangement with embedded matrix switch</title><description>Modems, data service units (109-111), application modules (108, 112, 114, 115) and other data communication devices (102-106), installed in a common equipment cabinet, are interconnected by way of a time division multiplexed bus (RB, WB, TSA, TYPE). Time slots assigned to the various devices recur at a number of regularly-spaced access periods across each time division multiplex frame. The rate at which the access periods occur and the total number of access periods that make up each frame are chosen in such a way as to accomodate a mix of devices having respective bus access rates wherein there is at least one pair of rates for which neither rate of the pair is a multiple of the other. The process of allocating access periods to the time slots is carried out using a known lemma to identify linear Diophantine equation solutions.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>MULTIPLEX COMMUNICATION</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1995</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLBySSxJVEjOz80tzctMTizJzM9TSCwqSsxLT81NzStRKM8syVBIzU1KTUlJTVHITSwpyqxQKAaKJmfwMLCmJeYUp_JCaW4GBTfXEGcP3dSC_PjU4oLE5NS81JJ41wADY1NjSxMzJ0NjIpQAAEt6Lxg</recordid><startdate>19950104</startdate><enddate>19950104</enddate><creator>DOUSKALIS, WILLIAM</creator><scope>EVB</scope></search><sort><creationdate>19950104</creationdate><title>Data communication arrangement with embedded matrix switch</title><author>DOUSKALIS, WILLIAM</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0353946B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>1995</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>MULTIPLEX COMMUNICATION</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>DOUSKALIS, WILLIAM</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DOUSKALIS, WILLIAM</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Data communication arrangement with embedded matrix switch</title><date>1995-01-04</date><risdate>1995</risdate><abstract>Modems, data service units (109-111), application modules (108, 112, 114, 115) and other data communication devices (102-106), installed in a common equipment cabinet, are interconnected by way of a time division multiplexed bus (RB, WB, TSA, TYPE). Time slots assigned to the various devices recur at a number of regularly-spaced access periods across each time division multiplex frame. The rate at which the access periods occur and the total number of access periods that make up each frame are chosen in such a way as to accomodate a mix of devices having respective bus access rates wherein there is at least one pair of rates for which neither rate of the pair is a multiple of the other. The process of allocating access periods to the time slots is carried out using a known lemma to identify linear Diophantine equation solutions.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record> |
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language | eng ; fre ; ger |
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subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY MULTIPLEX COMMUNICATION TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
title | Data communication arrangement with embedded matrix switch |
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